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®
Intel
855GME Chipset and Intel
2. Reference these signals to ground planes and avoid routing across power plane splits.
3. The number of routing layer transitions should be minimized. When layout constraints require
a routing layer transition, any such transition shall be accompanied with ground stitching vias
placed within 100 mils of the signal via with at least one ground via for every two signals
making a layer transition.
DBR# should be routed to the system reset logic (e.g., the SYSRST# signal of the 6300ESB) and
initiate the equivalent of a front panel reset commonly found in desktop systems. The 150 Ω to
240 Ω pull-up resistor should be placed within 1 ns of the ITP700FLEX connector.
Note: The CPU should not be power cycled when DBR# is asserted.
DBA# is an optional system signal that may be used to indicate to the system that the ITP/TAP port
is being used. When not implemented, this signal may be left as no connect. When implemented, it
shall be routed with a 150 Ω to 240 Ω pull-up resistor placed within 1 ns of the ITP700FLEX
connector. Refer to the ITP700 Debug Port Design Guide for more details on DBA# usage.
The ITP700FLEX VTT and VTAP pins should be shorted together and connected to the VCCP
(1.05 V) plane with a 0.1 µF decoupling capacitor placed within 0.1 inch of the VTT pins.
summarizes termination resistors values, placement, and voltages the ITP signals need to connect
to for proper operation for onboard ITP700FLEX debug port.
Table 19. Recommended ITP700FLEX Signal Terminations (Sheet 1 of 2)
Signal
TDI
TMS
TRST#
TCK
TDO
BCLK(p/n)
FBO
RESET#
BPM[5:0]#
DBA#
DBR#
80
®
6300ESB ICH Embedded Platform Design Guide
Termination Value
Termination Voltage
150 Ω ± 5%
VCCP (1.05 V)
39.2 Ω ± 1%
VCCP (1.05 V)
510-680 Ω ± 5%
GND
27.4 Ω ± 1%
GND
54.9 Ω ± 1% pull-up and
22.6 Ω ± 1% series
VCCP (1.05 V)
resistor
Connect to TCK pin of
Intel Pentium M/Celeron
N/A
M processor CPU
220 Ω ± 5% pull-up and
22.6 Ω ± 1% series
VCCP (1.05 V)
resistor
Not Required
VCC of target system
150-240 Ω ± 5%
recovery circuit
VCC of target system
150-240 Ω ± 5%
recovery circuit
Termination/Decap Location
Within ± 300 ps of the Intel
Pentium M/Celeron M processor
CPU TDI pin
Within ± 200 ps of the
ITP700FLEX connector TMS pin
Anywhere between Intel Pentium
M/Celeron M processor CPU and
ITP700FLEX connector
Within ± 200 ps of the ITP700
FLEX connector TCK pin
Within 1" of the ITP700FLEX
connector TDO pin
N/A
Within 0.5" of the ITP700FLEX
connector RESET# pin
Within 1 ns of the ITP700FLEX
connector DBA# pin
Within 1 ns of the ITP700FLEX
connector DBR# pin
Table 19
Notes
5
5
5
5
1,
5
2
1
1
3
4
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