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®
Intel
855GME Chipset and Intel
Figure 71. Command Routing for Topology
M C H
M C H
P in
The command signals shall be routed using a 2:1 trace spacing to trace width ratio for signals
within the DDR group, except clocks and strobes. Command signals shall be routed on inner layers
with minimized external traces.
5.4.6.2
Command Topology Routing Guidelines
Table 38
Table 38. Command Topology Routing Guidelines (Sheet 1 of 2)
Signal Group
Motherboard Topology
Reference Plane
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Minimum Spacing to Trace Width Ratio
Minimum Isolation Spacing to non-DDR Signals
Package Length P1
Trace Length P1+ L1
Trace Length P1+ L1+L2+L3
Trace Length L2 – Total DIMM to DIMM spacing
Trace Length L3 – Second DIMM Pad to Parallel
Resistor Pad
NOTES:
1. Recommended resistor values and trace lengths may change in a later revision of the design guide.
2. Power distribution vias from Rt to Vtt are not included in this count.
3. The overall maximum and minimum length to the DIMM must comply with clock length matching
requirements.
4. It is possible to route using three vias if one via is shared that connects to the DIMM1 pad and parallel
termination resistor.
P1
L 1
D IM M 0 P A D
presents the command topology routing guidelines.
Parameter
January 2007
®
6300ESB ICH Embedded Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
L 2
L 3
D IM M 1 P A D
Routing Guidelines
SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#
Daisy-Chain with Parallel Termination
Ground Referenced
55 Ω ± 15%
Inner layers: 4 mils
Outer layers: 5 mils
2:1 (e.g., 8 mil space to 4 mil trace)
20 mils
500 mils ± 250 mils
Refer to
Table 39
for exact package lengths.
Min = 2.0 inches
Max = 5.5 inches
Max = 7.5 inches
Max = 2.0 inches
Max = 1.5 inches
V tt
w
R t
143
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