Pci Data Signals Routing Summary; Pci 33 Mhz Clock Signals Routing Summary - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
®
Intel 6300ESB Design Guidelines
Table 91.

PCI Data Signals Routing Summary

Trace
Impedance
55 Ω ± 10%
Figure 120. PCI 33MHz Clock Layout Example
Table 92.

PCI 33 MHz Clock Signals Routing Summary

Trace
PCI Routing Requirements
Impedance
5 mils width, 50mils spacing
55 Ω ± 10%
(based on stackup
assumptions in
226
®
6300ESB ICH Embedded Platform Design Guide
PCI Routing Requirements
5 mils width, 7 mils spacing
(based on stackup
assumptions in Section 3.1)
CK409
W1
CK409
W4
®
Intel
W5
6300ESB
I/O Controller
Hub
Topology
2 -4
Devices
Section 3.1)
Topology
2 Slots
W1 = W2 = 0.5 inches,
R_IDSEL = 300 to 900 Ω
3 Slots
W1 = W2 = 0.5 inches,
R_IDSEL = 300 to 900 Ω
4 Slots
W1 = W2 = 0.5 inches,
R_IDSEL = 300 to 900 Ω
W2
R1
R2
Note: Clocks should be routed first.
Maximum Trace Length
W1 = 0.5 inches
W2 = W5 – 4.5"
W3 = 2.5 inches (Shown as a reference only)
W4 = 0.5 inches
W5 = May be as long as needed as long as
W2 is scaled accordingly
Maximum Trace Length
L1 L2 L3 L4
10 1.0
inches inch
10 1.0 1.0
inches inch inch
10 1.0 1.0
inches inch inch
W3
PCI
B1172-02
Resistor Values
R1 = 33 Ω
R2 = 33 Ω
1.0
inch