Sdq To Sdqs Mapping - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
Length matching is not required from the DIMM1 to the parallel termination resistors.
presents the length matching requirements between the SDQ, SDM, and SDQS signals within a
byte lane. Byte lane mapping is defined in
5.4.4.4

SDQ to SDQS Mapping

Table 33
signals, as required to do the required length matching.
Table 33. SDQ/SDM to SDQS Mapping
Signal
SDQ[7:0]
SDQ[15:8]
SDQ[23:16]
SDQ[31:24]
SDQ[39:32]
SDQ[47:40]
SDQ[55:48]
SDQ[63:56]
SDQ[71:64]
defines the mapping between the nine byte lanes, nine mask bits, and the nine SDQS
Mask
SDM[0]
SDM[1]
SDM[2]
SDM[3]
SDM[4]
SDM[5]
SDM[6]
SDM[7]
SDM[8]
January 2007
®
6300ESB ICH Embedded Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
Table 33.
Relative To
SDQS[0]
SDQS[1]
SDQS[2]
SDQS[3]
SDQS[4]
SDQS[5]
SDQS[6]
SDQS[7]
SDQS[8]
Figure 68
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