Pci Clock Group - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
Platform Clock Routing Guidelines
11.2.4

PCI Clock Group

The PCI clocks are series terminated and routed point-to-point as on the motherboard between the
CK409 and the PCI connectors with dedicated buffers for of the three slots. These clocks are
synchronous to the CLK33 clocks and are length tuned to compensate for the segment on the PCI
daughtercard.
clock group routing constraints.
Figure 141. PCI Clock Group Topology
CK409
Table 109. PCICLK Clock Group Routing Constraints
Class Name
Class Type
Topology
Reference Plane
Single Ended Trace Impedance (Zo)
Nominal Inner Layer Trace Width
Nominal Outer Layer Trace Width
Minimum Spacing (See exceptions below.)
Serpentine Spacing
Maximum Via Count
Series Termination Resistor Value
Trace Length Limits – L1
Trace Length Limits – L2
Trace Length Limits – L3
Total Length Range – L1 + L2
Length Matching Required
Clock to Clock Length Matching
Breakout Region Exceptions
256
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6300ESB ICH Embedded Platform Design Guide
Figure 141 depicts the PCI clock group topology.
Rs
L1
Parameter
Table 109
L2
Trace on Card
PCI
Connector
Definition
PCICLK
Individual Nets
Series Terminated Point to Point
Ground Referenced
55 Ω ±15%
4.0 mils
5.0 mils (pin escapes only)
20 mils
20 mils
4
33 Ω ±5%
Up to 500 mils (breakout segment)
1.5" to 8.0"
2.5" (as per PCI specification)
CLK33 – 2.5" (for nominal matching)
Yes (Pin to Pin)
±2.0"
PCICLK to PCICLK to (CLK33 – 2.5")
5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3"
presents the PCICLK
L3
PCI Device