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®
Intel
855GME Chipset and Intel
Layout Checklist
Table 155.
RTC Layout Checklist
#
5
RTC signals should be ground referenced.
13.3.6
PCI-X Layout Checklist
Table 156.
PCI-X Layout Checklist
#
Eight inches maximum to the first slot, then 1.5 inches to each
subsequent slot.
1
PCI-X clocks and loop-back clocks are scaled accordingly. (See
Section 9.10.1
Place the PXRCOMP pull-down resistor as close to the 6300ESB
2
as possible
3
IDSEL (See
Signals should be routed with 5 mils trace width and 12 mils
4
spacing. (edge-to-edge)
13.3.7
PCI Layout Checklist
Table 157.
PCI Layout Checklist
#
Ten inches maximum to the first slot, then one inch to each
subsequent slot.
1
PCI clocks and loop-back clocks are scaled accordingly (see
Figure 120
Signals should be routed with 5 mils trace width and 7 mils
2
spacing.(edge-to-edge)
Clock signals should be routed with 5 mils trace width and 50 mils
3
spacing.(edge-to-edge)
4
IDSEL (See
13.3.8
FWH Decoupling Layout Checklist
Table 158.
FWH Decoupling Layout Checklist
#
0.1 µF capacitors should be placed between the V
1
and the V
supply pins.
4.7 µF capacitors should be placed between the V
2
and the V
supply pins.
316
®
6300ESB ICH Embedded Platform Design Guide
Layout Recommendations
Layout Recommendations
through
Section 9.10.2
Section
9.10.2.)
Layout Recommendations
for more information).
Section 9.10.2
for more information.)
Layout Recommendations
ground pins, no less than 390 mils from the V
SS
ground pins, no less than 390 mils from the V
SS
for more information.)
supply pins
CC
CC
supply pins
CC
CC
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Comments
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