Intel 855GME Design Manual page 97

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Intel 855GME Chipset and Intel
connections between the DATA and ADDR sides of the Intel Pentium M/Celeron M processor
socket on the secondary side and the V
on the primary side (see Figure
In reality, the north and south sides of the V
planes in Layers 3, 5, and 6 as illustrated in
stitching vias next to the negative terminals of the nine capacitors on the north side with the
V stitching vias next to the negative terminals of the nine capacitors on the south side.
CC-CORE
Layers 3, 5, and 6 V
CC-CORE
processor FSB signals routed under the shadow of the Intel Pentium M/Celeron M processor socket
cavity. All the V
CC-CORE
to the internal V
CC-CORE
Special attention shall be given to not route any of the Intel Pentium M/Celeron M processor FSB
or any other signal in a way that would block V
pins of the Intel Pentium M/Celeron M processor socket in Layers 3, 5, and 6.
depicts how the V
CC-CORE
way from the SP capacitors and sense resistors in the north side of the V
south side of the 24 V
CC-CORE
continuous connection is imperative on all three internal layers because neither the primary nor the
secondary side V
CC-CORE
The remaining three 10 µF, 0805 capacitors are placed on the primary side immediately above the
shadow of the three 0805 capacitors on the secondary side and are placed at the same pitch
(90 mils) as shown in Figure 44
and 25 of the Intel Pentium M/Celeron M processor pins while one is on the side closest to signal
column 2. The area between these three capacitors may be efficiently used for VRM sense resistor
connections as illustrated in the primary side zoom view in
Special care shall be taken to provide a robust connection on the V
side from the sense resistors to the V
M/Celeron M processor socket. This robust connection is needed due to the presence of the GND
dog bones on the primary side. The specific arrangement of V
Figure 45 shall be closely followed to provide a robust connection to the V
ALL V BGA balls and vias on the primary side in the AF, AE, AD, AC, AB, AA, Y, W, V,
CC-CORE
and U signal rows of the Intel Pentium M/Celeron M processor socket connecting all the way up to
V stitching vias next to negative terminals of the nine 0805 capacitors placed under the
CC-CORE
socket cavity shadow.
Figure 47 depicts a magnified view of the recommended layout for the SP capacitor connections to
minimize their inductance on the secondary side (Layer 8) of the motherboard. The V
side of the capacitor has two V
capacitor within the shadow of the SP capacitor. These two V
GND vias with a 50-mil offset to reduce the inductance of the connection between the capacitor
and the plane. An additional pair of GND vias are placed 82 mils below the ground pad of the SP
capacitor (also under the shadow of the SP capacitor body) to allow efficient stitching of ground
planes on Layers 1, 2, 4, 7, and 8 in this area. Outside the shadow of the SP capacitors, the
V /GND via pairs of the SP capacitors are shared with the V
CC-CORE
0805 capacitors. The placement of additional vias is not advised because this results in excessive
perforation of the internal power planes due to the antipad voids. The pitch between the SP caps is
220 mils (or closer).
The layout concepts described in
effective resistance of 0.58 m Ω and an effective inductance of ~4 pH. Despite the use of multiple
power planes, this is still significant compared to the 3 m Ω load line target resistance and
®
6300ESB ICH Embedded Platform Design Guide
flood for all DATA, ADDR, and legacy side V
CCP
44).
CC-CORE
Figure
corridors use the fact that there are no Intel Pentium M/Celeron M
pins of the Intel Pentium M/Celeron M processor pin-map shall connect
planes of Layers 3, 5, and 6.
CC-CORE
planes on Layers 3, 5, and 6 make an uninterrupted connection all the
pins of the Intel Pentium M/Celeron M processor socket. This
floods make one continuous, robust connection from 'north to south.'
and Figure 45. Two are on the side closest to the signal column 24
corridor pins on the north side of the Intel Pentium
CC-CORE
vias placed 82 mils above the V
CC-CORE
Figure 44 through
January 2007
floods are bridged by means of V
46. Layers 3, 5, and 6 connect the V
connections to all the V
CC-CORE
Figure 45.
floods on the primary
CC-CORE
and GND vias as shown in
CC-CORE
CC-CORE
CC-CORE
vias are paired with two
CC-CORE
CC-CORE
Figure 47 result in an estimated V
pins
CCP
CC-CORE
CC-CORE
power
CC-CORE
Figure 46 also
corridor up to the
floods for
pin
CC-CORE
pad of the SP
/GND via pairs of the
CC-CORE
97