Intel 855GME Design Manual page 300

®
Intel 855GME Chipset and Intel
Layout Checklist
Table 148. Processor Layout Checklist (Sheet 1 of 7)
Checklist Items
1
A[31:3]#
ADSTB[1:0]#
DSTBN[3:0]#
DSTBP[3:0]#
DINV[3:0]#
5
D[63:0]#
REQ[4:0]#
ADS#
BNR#
BR0#
DBSY#
DRDY#
HIT#
HITM#
LOCK#
DPWR#
BPRI#
DEFER#
RS[2:0]#
8
TRDY#
7
RESET#
300
®
6300ESB ICH Embedded Platform Design Guide
Recommendations
® ®
Intel Pentium M Processor Front Side Bus Interface Signals
• Trace impedance = 55 Ω ± 15%.
• Use strip-line routing, referencing ground
planes above and below the signal layer.
• Route data strobes and data signals 4/12
with board trace length between 0.5 and 5.5
inches.
• Use GMCH die-pad to processor pin length
for all length matching operations.
• Length match data strobes of the same
2
group to within ± 25 mils of each other and to
3
the average length of their associated data
4
signal group.
• Route all data signals as groups, on the
same layer, and balance within group ± 100
6
mils with respect to the associated strobes.
• Route address strobes 4/12 and address
signals 4/8 with board trace length between
0.5 and 6.5 inches.
• Trace length match address strobes to ± 200
mils of average length of their associated
address signals group.
• Trace impedance = 55 Ω ± 15%.
• Use strip-line routing, referencing solid
ground planes.
• Route traces using 4/8 mils spacing with
board trace length between 1.0 and 6.5
inches.
• Trace length matching is not required for
common clock signals.
• Package length compensation is necessary
in determining minimum board trace length.
• When ITP700 Is Not Used:
• Trace impedance = 55 Ω ± 15%.
• Use strip-line routing, referencing solid
ground planes.
• Route traces using 4/8 mils spacing with
board trace length between 1.0 and 6.5
inches.
• Trace length matching is not required for
common clock signals.
• Package length compensation is necessary
in determining minimum board trace length.
Comments
• AGTL+ Source Synchronous
Signals.
• Refer to Section 4.1.3 for more
information.
• AGTL+ Common Clock Signals.
• Refer to Section 4.1.2 for more
information.
• Refer to ITP Section of this layout
checklist for treatment of RESET#
signal when implementing
ITP700FLEX debug port.
• AGTL+ Common Clock Signal.
• Refer to Section 4.1.6 for more
information.