Package Length Compensation - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
®
Intel Pentium
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Table 3. Intel Pentium
Common Clock Signal Internal Layer Routing Guidelines (Sheet 2 of 2)
Signal Names
CPU
DBSY#
DEFER#
DPWR#
DRDY#
HIT#
HITM#
LOCK#
RS0#
RS1#
RS2#
TRDY#
RESET#
† For topologies where an ITP700FLEX debug port is implemented, refer to
(CPURESET#) implementation details.
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4.1.2.1 Intel Pentium

Package Length Compensation

Trace length matching for the common clock signals is not required. However, package
compensation for the common clock signals is required for the minimum board trace. Refer to
Table 4 and the example for more details. Package length compensation shall not be confused with
length matching. Length matching refers to constraints on the minimum and maximum length
bounds of a signal group based on clock length, whereas package length compensation refers to the
process of adjusting out package length variance across a signal group.
All common clock signals are required to meet the minimum pad-to-pad requirement of 2.212
inches, based on ADS# (as this signal has the longest package lengths) implies a minimum
pin-to-pin motherboard trace length of 1.0 inches or more depending on package lengths. As a
result, additional motherboard trace is added to some of the shorter common clock nets on the
system board in order to meet the longest common clock signal total trace lengths from the die-pad
of the processor to the associated die-pad of the chipset.
For example:
ADS# = 997 mils board trace + 454 Intel Pentium M/Celeron M Processor PKG + 761 GMCH
PKG = 2212 pad-to-pad length.
BR0# = X mils board trace + 465 Intel Pentium M/Celeron M Processor PKG + 336 GMCH PKG
= 2212 pad-to-pad length.
Therefore: BR0# board trace = 2212 pad-to-pad length - 465 Intel Pentium M/Celeron M Processor
PKG - 336 GMCH PKG = 1411 pin-to-pin length.
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M/Celeron M Processor FSB Design and Power Delivery Guidelines
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M/Celeron M Processor System Bus
Transmission Line
GMCH
DBSY# Strip-line
DEFER# Strip-line
DPWR# Strip-line
DRDY# Strip-line
HIT# Strip-line
HITM# Strip-line
HLOCK# Strip-line
RS0# Strip-line
RS1# Strip-line
RS2# Strip-line
HTRDY# Strip-line
†
CPURESET# Strip-line
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M/Celeron
January 2007
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6300ESB ICH Embedded Platform Design Guide
Total Trace Length
Type
Min
(mils)
1159
1291
1188
1336
1303
1203
1198
1315
1193
1247
1312
1101
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M Processor Common Clock Signal
Nominal Width and
Impedance
Max
( Ω )
(inches)
6.5 55 ± 15%
6.5 55 ± 15%
6.5 55 ± 15%
6.5 55 ± 15%
6.5 55 ± 15%
6.5 55 ± 15%
6.5 55 ± 15%
6.5 55 ± 15%
6.5 55 ± 15%
6.5 55 ± 15%
6.5 55 ± 15%
6.5 55 ± 15%
Section 4.1.6 for RESET#
Spacing
(mils)
4 and 8
4 and 8
4 and 8
4 and 8
4 and 8
4 and 8
4 and 8
4 and 8
4 and 8
4 and 8
4 and 8
4 and 8
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