Asynchronous Signals; Asynchronous Agtl+ Nets - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
® ®
Intel Pentium M/Celeron
4.1.5

Asynchronous Signals

The following sections describe the topologies and layout recommendations for the asynchronous
open drain and CMOS signals found on the platform. All open drain signals listed in the following
sections must be pulled-up to VCCP (1.05 V). When any of these open drain signals are pulled-up
to a voltage higher than VCCP, the reliability and power consumption of the processor may be
affected. Therefore, it is very important to follow the recommended pull-up voltage for these
signals. All signals must meet the AC and DC specifications as documented in the Intel Pentium
M Processor Datasheet, Intel Pentium
Datasheet, or the Intel Celeron
Table 10. Asynchronous AGTL+ Nets
Signal
Names
IERR#
FERR#
THRMTRIP#
PROCHOT#
PWRGOOD
DPSLP#
LINT0/INTR
LINT1/NMI
SLP#
STPCLK#
IGNNE#
SMI#
A20M#
INIT#
†† Only supported by ICH4-M device. When not used, pull-up at CPU with 4.7 K Ω ± 5% resistor at VCCP.
58
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6300ESB ICH Embedded Platform Design Guide
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M Processor FSB Design and Power Delivery Guidelines
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M Processor Datasheet.
Description Topology #
Internal error 1A
Floating point
1B
error
Thermal
1B
sensor
Thermal
1C
sensor
System power
2A
good
††
Deep sleep
Local
2B
interrupts
Local
2B
interrupts
Sleep 2B
Processor
2B
stop clock
Ignore next
2B
numeric error
System
management 2B
interrupt
Address 20
2B
mask
Processor
3
initialize
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M Processor on the 90nm Process with 2MB L2 Cache
CPU I/O
Output
Type
O CPU
O CPU
O CPU
O CPU
AND
I
Gate
I
I 6300ESB
I 6300ESB
I 6300ESB
I 6300ESB
I 6300ESB
I 6300ESB
I 6300ESB
I 6300ESB
Output
Input Power
Buffer Input
Well
Type
System
AGTL+ Vcc_Receiver
Receiver
Main I/O
AGTL+ 6300ESB
(3.3 V)
System
AGTL+ Vcc_Receiver
Receiver
System
AGTL+ Vcc_Receiver
Receiver
OD
CPU N/A
CMOS
CPU
CMOS CPU N/A
CMOS CPU N/A
CMOS CPU N/A
CMOS CPU N/A
CMOS CPU N/A
CMOS CPU N/A
CMOS CPU N/A
CPU,
CMOS N/A, 3.3 V
FWH
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