Serial Ata Interface Layout Checklist - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
13.3.2

Serial ATA Interface Layout Checklist

Table 151.

Serial ATA Interface Layout Checklist

#
1
2
3
4
5
6
7
8
9
10
11
12
13
Layout Recommendations
Route SATA signals ground referenced.
Route SATA signals using a minimum of vias and corners. This
reduces signal reflections and impedance changes. Use a
maximum of two vias per trace. Vias should be matched on traces
within a transmit or receive pair.
When it becomes necessary to turn 90°, use two 45° turns or an
arc instead of making a single 90° turn. This reduces reflections
on the signal by minimizing impedance discontinuities.
Do not route SATA traces under crystals, oscillators, clock
synthesizers, magnetic devices or ICs that use and/or duplicate
clocks.
Route all traces over continuous planes (GND) with no
interruptions. Avoid crossing over anti-etch when possible.
Crossing over anti-etch (plane splits) increases inductance and
radiation levels by forcing a greater loop area. Likewise, avoid
changing layers with high-speed traces. (Applies to SATA signals,
high-speed clocks, as well as slower signals that might be
coupling to them.)
Keep SATA signals clear of the core logic set. High current
transients are produced during internal state transitions. These
transients may be difficult to filter out.
Keep traces at least 90 mils away from the edge of the plane (Vcc
or GND depending on which plane to which the trace is routed).
This helps prevent the coupling of the signal onto adjacent wires
and helps prevent free radiation of the signal from the edge of the
PCB.
Maintain parallelism between SATA differential signals with the
trace spacing needed to achieve 79.3 Ω differential impedance.
(Recommended: 7 mils width, 6 mils spacing.)
Minimize the length of high-speed clock and periodic signal traces
that run parallel to SATA signal lines to minimize crosstalk. The
minimum recommended spacing to clock signals is 100 mils.
Use 100 mils minimum spacing between SATA signal pairs and
other signal traces. This helps to prevent crosstalk.
SATA signal pair traces should be trace length matched. Max
trace length mismatch between SATA signal pair (such as TXN
and TXP) should be no greater than 10 mils.
Maximum length from the 6300ESB to the SATA connector should
not be greater than eight inches.
SATARBIASP and SATARBIASN should be routed 5 on 5 with a
single trace 500 mils or less to the 24.9 Ω 1% resistor to ground.
January 2007
®
6300ESB ICH Embedded Platform Design Guide
Layout Checklist
Comments
313