Itp_Clk Routing To Itp700Flex Connector - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
4.3.1.3

ITP_CLK Routing to ITP700FLEX Connector

A layout example for ITP_CLK/ITP_CLK# routing to an ITP700FLEX connector is shown in
Figure 37. The CK409 clock chip is mounted on the primary side of the motherboard and the
differential clock pair breaks out on the same side. The differential ITP clock pair routing requires
the use of a pair of 33 Ω ± 5 percent series resistors placed within 0.5 inches of the clock chip
output pins followed by a pair of 49.9 Ω ± 1 percent termination resistors to ground. Serpentining
of the ITP_CLK traces is performed to meet the ± 50 ps length matching requirement between
ITP_CLK and the sum of length L6 of the BCLK[1:0] lines and the additional length L2 of the
BPM#[5:0] signals in
layer through a via near the ITP700FLEX connector.
layout example.
Figure 37. ITP_CLK to ITP700FLEX Connector Layout Example
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6300ESB ICH Embedded Platform Design Guide
Figure 36. The ITP_CLK pair routing then switches back to the primary side
PRIMARY SIDE PRI MARY SIDE
49.9 49.9
33
33
CK 409 CK - 408
LAYER 6 LAYER 6
Figure 38 depicts the ITP700FLEX signals
ITP_CL ITP_CL
K K
ITP_CL ITP_CL
K ITP_CLK K ITP_CLK
# #
ITP700FLEX ITP700FLE
X Connect
X Connect
or
or