Agp Interface Signal Groups - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
AGP Port Design Guidelines
7.1.2

AGP Interface Signal Groups

The signals on the AGP interface are broken into three groups: 1X timing domain signals, 2X/4X
timing domain signals, and miscellaneous signals. Each group has different routing requirements.
In addition, within the 2X/4X timing domain signals, there are three sets of signals. All signals in
the 2X/4X timing domain must meet minimum and maximum trace length requirements, as well as
trace width and spacing requirements. Because of the multiplexed AGP/DVO interface, there are
trace length matching requirements within each set of 2X/4X signals, as well as between sets of
2X/4X signals. The signal groups are listed in following table.
Table 57. AGP 2.0 Signal Groups
1x Signals
CLK (3.3 V)
GRBF#
GWBF#
GST_[2:0]
GPIPE#
GREQ#
GGNT#
GPAR
GFRAME#
GIRDY#
GTRDY#
GSTOP#
GDEVSEL#
GAD_[31:0]
GC/BE_[3:0]#
GADSTB_[1:0]
Table 58. AGP 2.0 Data/Strobe Associations
AD[15:0] and C/BE[1:0]#
AD[31:16] and C/BE[3:2]#
SBA[7:0]
The routing guidelines for each group of signals (1X timing domain signals, 2X/4X timing domain
signals, and miscellaneous signals) will be addressed separately.
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82801DB ICH4 Embedded Platform Design Guide
2X signals include all 1X signals and:
GADSTB_[1:0]
GSBSTB
GAD_[31:0] signals and associated
GC/BE_[3:0]# signals are running at 2X
mode.
Data Associated Strobe in 1X
Strobes are not used in 1X mode. All
data is sampled on rising clock edges.
Strobes are not used in 1X mode. All
data is sampled on rising clock edges.
Strobes are not used in 1X mode. All
data is sampled on rising clock edges.
2x Signals
4X signals include all 1X signals and:
GADSTB_[1:0]
GADSTB_[1:0]#
GSBSTB
GSBSTB#
GAD_[31:0] signals and associated
GC/BE_[3:0]# signals are running at 4X
mode.
Strobes in 2X
4x Signals
Associated Associated
Strobes in 4X
AD_STB0,
AD_STB0
AD_STB0#
AD_STB1,
AD_STB1
AD_STB1#
SB_STB,
SB_STB
SB_STB#
Design Guide