Source Synchronous Signals General Routing Guidelines; Common Clock Topology; Signal Package Lengths And Minimum Board Trace Lengths - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
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Intel Pentium M/Celeron
Figure 7 depicts the common clock topology.
Figure 7. Common Clock Topology
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Table 4. Intel Pentium

Signal Package Lengths and Minimum Board Trace Lengths

Signal Names
CPU
ADS#
BNR#
BPRI#
BR0#
DBSY#
DEFER#
DPWR#
DRDY#
HIT#
HITM#
LOCK#
RS0#
RS1#
RS2#
TRDY#
RESET#
4.1.3

Source Synchronous Signals General Routing Guidelines

All source synchronous signals use an AGTL+ bus driver technology with on-die GTL termination
resistors connected in a point-to-point, Zo = 55 Ω controlled impedance topology between the Intel
Pentium M/Celeron M Processor and the GMCH. No external termination is needed on these
signals. Source synchronous Intel Pentium M/Celeron M Processor FSB address signals operate at
a double-pumped rate of 200 MHz while the source synchronous processor FSB data signals
operate at a quad-pumped rate of 400 MHz. High speed operation of the source synchronous
signals requires careful attention to their routing considerations. The following guidelines shall be
strictly adhered to, to ensure robust high-frequency operation of these signals.
42
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6300ESB ICH Embedded Platform Design Guide
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M Processor FSB Design and Power Delivery Guidelines
Processor
Pad
Package trace
Motherboard PCB trace
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M/Celeron M Processor and Intel
Package Length
GMCH CPU
ADS# 454
BNR# 506
BPRI# 424
BR0# 336
DBSY# 445
DEFER# 349
DPWR# 506
DRDY# 529
HIT# 420
HITM# 368
HLOCK# 499
RS0# 576
RS1# 524
RS2# 451
HTRDY# 389
CPURESET# 455
Length L1
GMCH
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GMCH FSB Common Clock
Total Pad-to-Pad Min.
Length Requirements L1
GMCH
761 2212
408 2212
573 2212
465 2212
608 2212
572 2212
518 2212
347 2212
489 2212
641 2212
515 2212
321 2212
495 2212
514 2212
511 2212
656 2212
Pad
Minimum
Routable Board
Trace Length
997
1298
1215
1411
1159
1291
1188
1336
1303
1203
1198
1315
1193
1247
1312
1101