Clk14 Clock Group; Clk14 Clock Group Topology; Clk14 Clock Group Routing Constraints - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
11.2.5

CLK14 Clock Group

The 14 MHz clocks are series terminated and routed point-to-point on the motherboard. A single
clock output is shared between the two loads. These clocks are length tuned to each other but are
not synchronous with any other clocks.
Table 110
Figure 142. CLK14 Clock Group Topology
C K 409
Table 110. CLK14 Clock Group Routing Constraints
Class Name
Class Type
Topology
Reference Plane
Single Ended Trace Impedance (Zo)
Nominal Inner Layer Trace Width
Nominal Outer Layer Trace Width
Minimum Spacing (See exceptions below.)
Serpentine Spacing
Maximum Via Count
Series Termination Resistor Value
Trace Length Limits – L1
Trace Length Limits – L2A, L2B
Total Length Range – L1 + L2A & L1 + L2B
Length Matching Required
Clock to Clock Length Matching
Breakout Region Exceptions
presents the CLK14 clock group routing constraints.
L1
Parameter
January 2007
®
6300ESB ICH Embedded Platform Design Guide
Platform Clock Routing Guidelines
Figure 142 depicts the CLK14 clock group topology.
R s
L2 A
R s
L2B
S IO , Intel® 6300ES B _U AR T
CLK14
Individual Nets
Dual Series Terminated Point to Point
Ground Referenced
55 Ω ±15%
4.0 mils
5.0 mils (pin escapes only)
20 mils
20 mils
4 (per driver/receiver path)
33 Ω ±5%
Up to 500 mils
2.0" to 8.5"
2.0" to 9.0"
Yes (Pin to Pin)
±500 mils
CLK14A to CLK14B
5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3"
Intel® 6300E S B , Audio
Definition
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