Ddr Dimm Interface Checklist; Reference Voltage Level For Smvref - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
Schematic Checklist Summary
Figure 150. Reference Voltage Level for SMVREF
50 +/ - 1%
50 +/ - 1 %
12.3.1.2

DDR DIMM Interface Checklist

Table 122
Table 122. DDR DIMM Interface Checklist
Pin Name
NC (FETEN)
(pin 167)
CS[3:2]#
(pin163, 71)
BA2 (pin 113)
VREF (pin 1)
VDD[9:1]
VDDSPD
SA[2:1]
SA0
VSS[22:1]
NC
(pin 10)
SDA/SCL
NC (pin 90)
A13
(pin 103)
VDDQ[16:1]
VDDID (pin 82)
NC[4:1] (pins
9,101,102,173)
274
®
6300ESB ICH Embedded Platform Design Guide
V _2P 5 _S M
presents the DDR DIMM interface checklist.
Configuration
Connected to 82855GME
SMVREF signal
Connect to V_2P5_SM
Connect to V_2P5_CORE
Connect to GND
DIMM 0: connect to GND
DIMM 1: connect to
V_2P5_SM
Connect to GND
Connect to the 6300ESB
SMBUS and SMLINK
through isolation circuitry.
Connect to V_2P5_SM
+
S M V R EF
-
0.1 uF
Signal may be left as NC (Not Connected).
Signal may be left as NC.
Signal may be left as NC.
Signal voltage level = V_2P5_SM/2.
Place a 0.1µF cap by GMCH, DIMM 0, and DIMM 1
pins.
Power must be provided during S3.
These lines are used for strapping the SPD address
for each DIMM.
These lines are used for strapping the SPD address
for each DIMM.
Signal may be left as NC.
Signal may be left as NC.
Signal may be left as NC.
Signal may be left as NC.
Signal may be left as NC.
G M C H
S MV R E F _0
Notes
√