Intel 855GME Design Manual page 276

Chipset, ich embedded platform
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®
Intel
855GME Chipset and Intel
Schematic Checklist Summary
Table 124. FSB Checklist (Sheet 2 of 2)
Pin Name
BCLK,
BCLK#
HDSTBN[3:0]#
HDSTBP[3:0]#
DINV[3:0]#
CPURST#
HD[63:0]#
DPWR#
DPSLP#
HXSWING
HYSWING
HXRCOMP
HYRCOMP
HDVREF[2:0]
HAVREF
HCCVREF
276
®
6300ESB ICH Embedded Platform Design Guide
System
Pull-up/Pull-down
Refer to the CK409
Checklist for CPU[0],
CPU[0]#, CPU[1],
Connect to CK409.
CPU[1]#, CPU[2], and
CPU[2]#.
Connect directly to processor (DSTBN[3:0]# signals).
Connect directly to processor (DSTBP[3:0]# signals).
Connect directly to processor (DINV[3:0]# signals).
220 Ω 6% pull-up to
VCCP. 22.6 Ω 1%
series to ITP (pin 12).
Connect to processor (RESET# signal) and ITP (if
®
Refer to the Pentium
M
implemented).
Processor Checklist for
RESET#.
Connect directly to processor (D[63:0]# signals).
Connect directly to processor (DPWR# signal).
1 K Ω pull-up to VCCP at
GMCH.
Used only with the ICH4-M.
4.7 K Ω pull-up to VCCP
The 6300ESB does not provide this signal.
at CPU.
301 Ω 1% pull-up to
Signal voltage level = 1/3 of VCCP. C1a = 0.1 µF.
VCCP
C1b=0.1 µF.
150 Ω 1% pull-down to
Refer to
GND
301 Ω 1% pull-up to
Signal voltage level = 1/3 of VCCP. C1a=0.1 µF.
VCCP
C1b=0.1 µF.
150 Ω 1% pull-down to
Refer to
GND
27.4 Ω 1% pull down to
One pull-down resistor where trace shall be 10 mil wide
GND
with 20 mil spacing. Refer to
27.4 Ω 1% pull down to
One pull-down resistor where trace shall be 10 mil wide
GND
with 20 mil spacing. Refer to
49.9 Ω 1% pull-up to
VCCP
Signal voltage level = 2/3 of VCCP. Need one 0.1 µF cap
100 Ω 1% pull-down to
and one 1 µF cap near voltage divider.
GND
49.9 Ω 1% pull-up to
VCCP
Signal voltage level = 2/3 of VCCP. Need one 0.1 µF cap
100 Ω 1% pull-down to
and one 1 µF cap for voltage divider.
GND
49.9 Ω 1% pull-up to
Signal voltage level = 2/3 of VCCP. Need one 0.1 µF cap
VCCP
and one 1 µF cap for voltage divider.
100 Ω 1% pull-down to
GND
Notes
Figure
151.
Figure
151.
Section
4.8.3.2.
Section
4.8.3.2.

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