Smbus Architecture & Design Considerations; Smbus Design Considerations; General Design Issues / Notes; Smbus 2.0/Smlink Interface - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
®
Intel 6300ESB Design Guidelines
Both the SMBus Host Controller and the SMBus Slave Interface obey the SMBus 1.0 protocol, so
the two interfaces may be externally wire-ORed together to allow an external management ASIC
(such as Intel 82562EM/82562EX 10/100 Mbps Platform LAN Connect) to access targets on the
SMBus as well as the 6300ESB Slave interface. Additionally, the 6300ESB supports slave
functionality, including the Host Notify protocol, on the SMLink pins.
Figure 116.

SMBUS 2.0/SMLink Interface

Host Controller
and Slave Interface
I/O Controller
Note: Intel does not support access of the 6300ESB SMBus Slave Interface by the 6300ESB SMBus Host
Controller. Refer to the Intel
descriptions of the SMLink and SMBus interface.
9.8.1 SMBus Architecture & Design Considerations
9.8.1.1

SMBus Design Considerations.

There is not a single SMBus design solution that will work for all platforms. One must consider the
total bus capacitance and device capabilities when designing SMBus segments. Routing SMBus to
the PCI slots makes the design process even more challenging since they add so much capacitance
to the bus. This extra capacitance has a large affect on the bus time constant which in turn affects
the bus rise and fall times.
Primary considerations in the design process are:
•
Device class (High/Low power). Most designs use primarily High Power Devices.
•
Mixed Power Architecture. If there are devices that must run in S3, special considerations
must be made (see
•
Amount of V
9.8.1.2

General Design Issues / Notes

Regardless of the architecture used, there are some general considerations.
•
The pull-up resistor size for the SMBus data and clock signals is dependent on the bus load
(this includes all device leakage currents). Generally, the SMBus device that may sink the least
222
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6300ESB ICH Embedded Platform Design Guide
SPD Data
SMBus
®
Intel
6300ESB
Hub SMLink
®
6300ESB I/O Controller Hub Datasheet for full functionality
Section 9.8.1.3).
_ current available (i.e., minimizing load of V
CC SUSPEND
SMBCLK
SMBDATA
SMLink0
SMLink1
Microcontroller
Network
Interface Card
on PCI Bus
Temperature on
Thermal Sensor
Motherboard
LAN Controller
on PCI Bus
_
CC SUSPEND
B1168-02
)
.