Intel 855GME Design Manual page 68

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Intel 855GME Chipset and Intel
Because the input buffer trip point is set by the 2/3*VCCP on GTLREF to allow tracking of VCCP
voltage fluctuations, no decoupling shall be placed on the GTLREF pin. The node between R1 and
R2 (GTLREF) shall be connected to the GTLREF pin of the Intel Pentium M/Celeron M processor
with Zo = 55 Ω trace shorter than 0.5 inches. Space any other switching signals away from
GTLREF with a minimum separation of 25 mils. Do not allow signal lines to use the GTLREF
routing as part of their return path (i.e., do not allow the GTLREF routing to create splits or
discontinuities in the reference planes of the Intel Pentium M/Celeron M processor system bus
signals).
Previous revisions of design guides and the Intel Pentium M/Celeron M processor pin-map
contained references to three additional pins devoted to the delivery of the GTLREF reference
voltage to the package. These three pins have been renamed into RSVD pins and are required to be
left as no connects on the platform. RSVD signal pins E26, G1, and AC1 are to be left unconnected
on Intel Pentium M/Celeron M processor-based systems.
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Figure 27. Intel Pentium
A recommended layout of GTLREF for the Intel Pentium M/Celeron M processor is shown in
Figure 28. To avoid interaction with Intel Pentium M/Celeron M processor FSB routing and power
delivery, GTLREF's R1 and R2 components are placed next to each other on the primary side of
the motherboard and connected with a Zo = 55 Ω, 370 mil long trace to the GTLREF pin on the
Intel Pentium M/Celeron M processor, which meets the 0.5-inch maximum length requirement.
The BGA ball lands on the primary side for the RSVD signal pins E26, G1, and AC1 are shown for
illustrative purposes and are not routed.
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6300ESB ICH Embedded Platform Design Guide
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M/Celeron M Processor GTLREF Voltage Divider Network
+ V C C P
R 1 R 1
1K 1K
1% 1%
G T L R E F
R 2 R 2
2K 2K
1% 1%
< 0.5" < 0.5"
Z o= 55 Ω trace
G T L R E G T L R E F
F (p in
(pin A D 26 )
A D 2 6)
® B an ia s ®
In tel P en tiu m M Pro ce sso r
R S V
R S V D
(pin E 2 6)
(pin
D
R S V
R S V D
(pin
(p in A C 1)
D
A C 1)
R S V D
(pin G 1)
D