Table of Contents
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®
Intel
855GME Chipset and Intel
9.2
IDE Interface..................................................................................................................... 194
9.2.1
Cabling................................................................................................................. 194
9.3
Cable Detection for Ultra ATA/66 and Ultra ATA/100....................................................... 195
9.3.1
Combination Host-Side/Device-Side Cable Detection......................................... 195
9.3.2
Device-Side Cable Detection............................................................................... 196
9.3.3
Primary IDE Connector Requirements ................................................................ 198
9.3.4
Secondary IDE Connector Requirements............................................................ 199
9.4
AC'97................................................................................................................................ 200
9.4.1
AC'97 Routing...................................................................................................... 203
9.4.2
Motherboard Implementation............................................................................... 204
9.4.2.1
9.4.3
SPKR Pin Consideration...................................................................................... 205
9.4.4
AC_SDOUT Pin Consideration............................................................................ 206
9.4.5
SIU0_DTR# Pin Consideration ............................................................................ 206
9.5
Communication Network Riser ......................................................................................... 206
9.5.1
AC'97 Audio Codec Detect Circuit and Configuration Options ............................ 207
9.5.1.1
9.5.2
CNR Routing Summary ....................................................................................... 209
9.6
USB 2.0 ............................................................................................................................ 210
9.6.1
Layout Guidelines ................................................................................................ 210
9.6.1.1
9.6.1.2
9.6.1.3
9.6.1.4
9.6.1.5
9.6.1.6
9.6.2
Plane Splits, Voids and Cut-Outs (Anti-Etch) ...................................................... 213
9.6.2.1
9.6.2.2
9.6.3
USB Power Line Layout Topology....................................................................... 214
9.6.4
EMI Considerations ............................................................................................. 214
9.6.4.1
9.6.5
ESD ..................................................................................................................... 215
9.6.6
Front Panel Solutions .......................................................................................... 216
9.6.6.1
9.6.6.2
9.6.6.3
9.7
Low Pin Count (LPC) Interface. ........................................................................................ 219
9.7.1
General Routing and Placement.......................................................................... 220
9.7.2
LPC Trace Length Matching ................................................................................ 220
9.7.3
LPC Interface Routing Guidelines ....................................................................... 220
9.8
SMBus 2.0/SMLink Interface ............................................................................................ 221
9.8.1
SMBus Architecture & Design Considerations .................................................... 222
9.8.1.1
9.8.1.2
9.8.1.3
9.8.1.4
9.9
PCI.................................................................................................................................... 224
9.9.1
PCI Routing Summary ......................................................................................... 224
9.9.2
PIRQ Routing Example........................................................................................ 227
9.10
PCI-X Design Guidelines .................................................................................................. 228
8
®
6300ESB ICH Embedded Platform Design Guide
Valid Codec Configurations ................................................................. 205
General Routing and Placement.......................................................... 210
USB 2.0 Trace Separation ................................................................... 211
USB BIAS Connections ....................................................................... 211
USB 2.0 Termination............................................................................ 212
USB 2.0 Trace Length Pair Matching .................................................. 212
USB 2.0 Trace Length Guidelines ....................................................... 212
VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch) ............................. 213
GND Plane Splits, Voids, and Cut-Outs (Anti-Etch)............................. 214
Common-Mode Chokes ....................................................................... 215
Internal USB Cables ............................................................................ 216
Motherboard/PCB Mating Connector................................................... 217
Front Panel Connector Card ................................................................ 218
SMBus Design Considerations. ........................................................... 222
General Design Issues / Notes ............................................................ 222
High Power/Low Power Mixed Architecture......................................... 223
Calculating the Physical Segment Pull-Up Resistor ............................ 223
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