Trace Length Mismatch Requirements; Agp Clock Skew - Intel 855GME Design Manual

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Intel
855GME Chipset and Intel
7.2.2.3

Trace Length Mismatch Requirements

Table 61. AGP 2.0 Data Lengths Relative to Strobe Length
Max Trace Length
< 6 in
The trace length minimum and maximum (relative to strobe length) should be applied to each set of
2X/4X timing domain signals independently. If AD_STB0 is 5 inches and ADSTB0# is 5.01
inches, then AD[15:0] and C/BE[1:0] must be between 4.91 inches and 5.1 inches. However,
AD_STB1 and ADSTB1# can be 3.5 inches and 3.51 inches (and therefore AD[31:16] and C/
BE#[3:2] must be between 3.41 inches and 3.6 inches). In addition, all 2X/4X timing domain
signals must meet the maximum trace length requirements.
All signals should be routed as strip lines (inner layers).
All signals in a signal group should be routed on the same layer. Routing studies have shown
that these guidelines can be met. The trace length and trace spacing requirements must not be
violated by any signal. Trace length mismatch for all signals within a signal group should be as
close to 0 inches as possible to provide optimal timing margin.
The strobe pair must be length matched to less than ± 0.01 inches (that is, a strobe and its
compliment must be the same length within ± 0.01 inches).
Table 62
Table 62. AGP 2.0 Routing Guideline Summary
Signal
1X Timing
Domain
2X/4X Timing
Domain Set#1
2X/4X Timing
Domain Set#2
2X/4X Timing
Domain Set#3
7.2.3

AGP Clock Skew

The maximum total AGP clock skew between the GMCH and the graphics component is 1 ns for
all data transfer modes. This 1 ns includes skew and jitter, which originates on the motherboard,
add-in module (if used), and clock synthesizer. Clock skew must be evaluated not only at a single
threshold voltage, but also at all points on the clock edge that falls in the switching range. The 1 ns
skew budget is divided such that the motherboard is allotted 0.9 ns of clock skew (the motherboard
designer shall determine how the 0.9 ns is allocated between the board and the synthesizer).
Design Guide
Trace Spacing
1:2
shows the AGP 2.0 routing summary.
Trace
Maximum
Spacing
Length
mil traces)
10 in
4 mils
6 in
8 mils
6 in
8 mils
6 in
8 mils
®
82801DB ICH4 Embedded Platform Design Guide
Strobe Length
Min Trace Length
X
X - 0.1 in
Length
(4
Relative To
Mismatch
No Requirement N/A
AD_STB0 and
± 0.1 in
AD_STB0#
AD_STB1 and
± 0.1 in
AD_STB1#
SB_STB and
± 0.1 in
SB_STB#
AGP Port Design Guidelines
Max Trace Length
X + 0.1 in
Notes
None
AD_STB0, AD_STB0#
must be the same length
AD_STB1, AD_STB1#
must be the same length
SB_STB, SB_STB#
must be the same length
177

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