System Memory Design Guidelines (Ddr-Sdram); Introduction - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
System Memory Design Guidelines
(DDR-SDRAM)
5.1

Introduction

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The Intel
of SSTL-2 compatible signals. These SSTL-2 compatible signals have been divided into several
signal groups: data, control, command, CPC, clock, and feedback signals.
different signal grouping. Refer to the Intel
Controller Hub (GMCH) Datasheet for details on the signals listed.
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Table 27. Intel 855GME Chipset DDR Signal Groups
Group
Clocks
Data
Control
Command
CPC
Feedback
855GME Chipset Double Data Rate (DDR) SDRAM system memory interface consists
Signal Name
SCK[5:0]
SCK[5:0]#
SDQ[63:0]
SDQ[71:64]
SDQS[8:0]
SDM[8:0]
SCKE[3:0]
SCS[3:0]#
SMA[12:6,3,0]
SBA [1:0]
SRAS#
SCAS#
SWE#
SMA[5,4,2,1]
SMAB[5,4,2,1]
RCVENOUT#
RCVENIN#
January 2007
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6300ESB ICH Embedded Platform Design Guide

System Memory Design Guidelines (DDR-SDRAM)

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855GM/855GME Chipset Graphics and Memory
Description
DDR-SDRAM differential clocks - (three per DIMM)
DDR-SDRAM inverted differential clocks - (three per DIMM)
Data bus
Check bits for ECC function
Data strobes
Data mask
Clock enable - (one per Device Row)
Chip select - (one per Device Row)
Memory address bus
Bank select
Row address select
Column address select
Write enable
Command per clock (DIMM0)
Command per clock (DIMM1)
Receive enable output (no external connection)
Receive enable input (no external connection)
5
Table 27 summarizes the
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