Resistive Compensation - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
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Figure 29. Intel Pentium

Resistive Compensation

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Figure 30. Intel Pentium
Resistive Compensation
The recommended layout of the Intel Pentium M/Celeron M processor COMP[3:0] resistors is
illustrated in
routing on internal layers and VCCA power delivery on the primary side, Layer 1, COMP[1:0]
resistors are placed on the secondary side. Ground connections to the COMP[1:0] resistors use a
small ground flood on the secondary side layer and connect only with a single GND via to stitch
the GND planes. The compact layout as shown in
perforation of the V
with an ~18 mil wide (Zo = 27.4 Ω) and 160 mil long trace to COMP0. Necking down to 14 mils is
allowed for a short length to pass in between the dog bones. The 54.9 Ω resistor connects with a
regular 5 mil wide (Zo = 55 Ω) and 267 mil long trace to COMP1. Placement of COMP[1:0] on the
primary side is possible as well. An alternative placement implementation is shown in
To minimize motherboard space usage and produce a robust connection, the COMP[3:2] resistors
are also placed on the secondary side
18 mil wide (Zo = 27.4 Ω) and 260 mil long trace to COMP2. Necking down to 14 mils is allowed
for a short length to pass in between the dog bones. Notice that the COMP2
dog bone trace connection on the primary side is also widened to 14 mils to meet the Zo = 27.4 Ω
characteristic impedance target. The right side of
resistor connects with a regular 5 mil wide (Zo = 55 Ω) and 100 mil long trace to COMP3. The
ground connection of COMP[3:2] is done with a small flood plane on the secondary side that
connects to the GND vias of pins AA1 and Y2 of the Intel Pentium M/Celeron M processor
pin-map. This is done to avoid via interaction with the Intel Pentium M/Celeron M processor FSB
routing on Layer 3 and Layer 6.
For COMP2 and COMP0, it is extremely important that 18 mil wide dog bone connections on the
primary side and 18-mil wide traces on the secondary sides be used to connect the signals to
compensation resistors on the secondary side, as shown in
and traces are used to achieve the Zo = 27.4 Ω target to ensure proper operation of the Intel
Pentium M/Celeron M processor FSB. Refer to
70
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6300ESB ICH Embedded Platform Design Guide
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M/Celeron M Processor COMP[2] and COMP[0]
COMP[0]
27.4 Ω ±1%
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M/Celeron M ProcessorCOMP[3] and COMP[1]
COMP[3]
54.9 Ω ±1%
Figure 31. To avoid interaction with Intel Pentium M/Celeron M processor FSB
plane power delivery.
CCP
(Figure
COMP[2]
27.4 Ω ±1%
COMP[1]
54.9 Ω ±1%
Figure 31 shall be used to avoid excessive
illustrates how a 27.4 Ω resistor connects
Figure 31
31, right side). A 27.4 Ω resistor connects with an
also illustrates how the 54.9 Ω ± 1%
Figure 31
Figure 33. The 18-mil wide dog bones
Figure 29 for more details.
Figure 32.
(Figure 31, left side)