Pentium ® M/Celeron ® M Processor Reset# Signal; Voltage Translation Circuit; Processor Reset# Signal Routing Topology With No Itp700Flex Connector - Intel 855GME Design Manual

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Intel
855GME Chipset and Intel
Figure 22. Voltage Translation Circuit
4.1.6
Pentium
The RESET# signal is a common clock signal driven by the GMCH CPURESET# pin. In a
production system where no ITP700FLEX debug port is implemented, a simple point-to-point
connection between the CPURESET# pin of the GMCH and the Intel Pentium M/Celeron M
processor's RESET# pin is recommended (see
buffers on both the processor and the GMCH provide proper signal quality for this connection.
This is the same case as for the other common clock signals listed
interconnect shall be limited to minimum of 1 inch and maximum of 6.5 inches.
Figure 23. Processor RESET# Signal Routing Topology With NO ITP700FLEX Connector
For a system that implements an ITP700FLEX debug port a more elaborate topology is required to
ensure proper signal quality at both the processor signal pad and the ITP700FLEX input receiver.
In this case the topology illustrated in
from the GMCH shall fork out (do not route one trace from GMCH pin and then T-split) towards
the processor's RESET# pin as well as toward the Rtt and Rs resistive termination network placed
next to the ITP700FLEX debug port connector. Rtt (220 Ω + 5 percent) pulls-up to the VCCP
voltage and is placed at the end of the L2 line that is limited to a 6-inch maximum length.
Rs (22.6 Ω ± 1 percent) must be placed right next to Rtt to minimize routing between them in the
vicinity of the ITP700FLEX connector to limit the L3 length to less than 0.5 inches. ITP700FLEX
operation requires the matching of L2 + L3 - L1 length to the length of the BPM[4:0]# signals
length within ± 50 ps. See
Section 4.1.1.4
routing length summary and termination resistor values.
64
®
6300ESB ICH Embedded Platform Design Guide
1.3 KΩ
±5%
330 Ω
±5%
From Driver
Rs
®
®
M/Celeron
CPU
Section 4.3
for more details on signal propagation time to distance correlation. See
3.3 V
330 Ω
±5%
R1
Q2
Q1
3904
M Processor RESET# Signal
Figure
23). On-die termination of the AGTL+
L1
Figure 24
shall be implemented. The CPURESET# signal
for more details on ITP700FLEX signal routing and
3.3 V
R2
To Receiver
3904
Section
4.1.2. Length L1 of this
GMCH
Table 17
for

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