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®
Intel
855GME Chipset and Intel
Schematic Checklist Summary
Figure 149. Voltage Translation Circuit for PROCHOT# (for Intel
Processor)
12.1.2
In Target Probe (ITP)
Table 116
Table 116. In Target Probe (ITP)
Pin Name
BPM[5:0]#
DBR#
RESET#
FBO
TCK
TDI
TDO
TMS
TRST#
VTAP,
VTT[1:0]
268
®
6300ESB ICH Embedded Platform Design Guide
1.3K
330ohm
+/-5%
From Driver
5%
Rs
presents the In Target Probe (ITP) information.
System
Termination
Pull-up/Pull-down
Resistor ( Ω )
150-240 Ω pull-up
to VCC3
220 Ω ± 5 % pull-up
22.6 Ω ± 1%
to VCCP when
from pull-up to
using ITP700FLEX
ITP700FLEX
27.4 Ω ± 1%
pull-down to GND
150 Ω pull-up to
VCCP
22.6 Ω ± 1%
54.9 Ω ± 1% pull-up
from pull-up to
to VCCP
ITP700FLEX
39.2 Ω ± 1% pull-up
to VCCP
680 Ω pull-down to
GND
Connect to VCCP
3.3V
330ohm
+/-5%
R1
5%
+/-5%
Q2
555%
Q1
3904
Series
Connect to processor directly.
When using ITP on interposer card, DBR# shall
also be connected to DBR# pin at the processor.
The 150-240 Ω pull-up resistor shall be placed
within 1 ns of the ITP700FLEX connector. The
CPU shall not be power cycled when DBR# is
asserted.
Refer to the RESET# notes in
Connect to TCK pin of processor. Refer to
Section 4.3.1.1
for layout details.
Connect to processor, with resistor placed by ITP.
Refer to
Section 4.3.1.1
Connect to processor with resistor placed by the
processor. Refer to
details.
Connect to processor with resistors placed by ITP.
When ITP not used, this signal may be left as NC.
Connect to processor with resistor placed by ITP.
Connect to processor with resistor located
anywhere between processor and ITP.
One 0.1 µF decoupling cap near ITP is required.
Refer to
Section 4.3.1.1
®
®
Pentium
M/Celeron
3.3V
R2
To Receiver
3904
Notes
Table
115.
for layout details.
Section 4.3.1.1
for layout
for layout details.
®
M
√
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