Intel 855GME Design Manual page 13

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Intel 855GME Chipset and Intel
39 ITP_CLK to CPU ITP Interposer Layout Example ...................................................................... 85
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40 Intel Pentium M/Celeron
Power Delivery and Decoupling.................................................................................................. 87
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41 Intel Pentium M/Celeron
Routing Example ........................................................................................................................ 88
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42 Intel Pentium M/Celeron
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43 Intel Pentium M/Celeron
and Decoupling Concept Example (Option #4) .......................................................................... 93
44 VCC-CORE Power Delivery and Decoupling Example -
Option 4 (Primary and Secondary Side Layers) .........................................................................98
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45 Intel Pentium M/Celeron
'North Corridor' Zoom-in View .................................................................................................... 99
46 VCC-CORE Power Delivery and Decoupling Example - Option 4 (Layers 3, 5, and 6)............. 99
47 Recommended SP Cap Via Connection Layout (Secondary Side Layer) ................................ 100
48 Platform Power Delivery Map ................................................................................................... 104
49 GMCH Power-up Sequence ..................................................................................................... 105
50 Example V5REF/3.3 V Sequencing Circuitry............................................................................106
51 Example for Minimizing Loop Inductance ................................................................................. 107
52 DDR Power Delivery Block Diagram ........................................................................................110
53 GMCH SMRCOMP Resistive Compensation ........................................................................... 111
54 GMCH System Memory Reference Voltage Generation Circuit ............................................... 112
55 GMCH HDVREF[2:0] Reference Voltage Generation Circuit ................................................... 113
56 GMCH HAVREF Reference Voltage Generation Circuit .......................................................... 113
57 GMCH HCCVREF Reference Voltage Generation Circuit........................................................ 114
58 Primary Side of the Motherboard Layout .................................................................................. 114
59 Secondary Side of the Motherboard Layout ............................................................................. 115
60 GMCH HXRCOMP and HYRCOMP Resistive Compensation ................................................. 115
61 GMCH HXSWING and HYSWING Reference Voltage Generation Circuit...............................116
62 Example Analog Supply Filter................................................................................................... 116
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63 Intel 6300ESB Power Delivery Example ................................................................................ 118
64 DDR Clock Routing Topology (SCK[5:0]/SCK[5:0]#)................................................................126
65 DDR Clock Trace Length Matching Diagram............................................................................129
66 Data Signal Routing Topology .................................................................................................. 131
67 SDQS to Clock Trace Length Matching Diagram .....................................................................134
68 SDQ/SDM to SDQS Trace Length Matching Diagram ............................................................. 136
69 Control Signal Routing Topology .............................................................................................. 139
70 Control Signal to Clock Trace Length Matching Diagram .........................................................141
71 Command Routing for Topology ...............................................................................................143
72 Topology Command Signal to Clock Trace Length Matching Diagram .................................... 145
73 CPC Control Signal Routing Topology ..................................................................................... 147
74 CPC Signals to Clock Length Matching Diagram .....................................................................149
75 GMCH DAC Routing Guidelines ...............................................................................................155
76 Rset Placement ........................................................................................................................ 156
77 DAC R, G, B Routing and Resistor Layout Example ................................................................157
78 DVOB and DVOC Simulations Model....................................................................................... 167
79 Driver-Receiver Waveforms Relationship Specification ........................................................... 168
80 DVO Enabled Simulation Model ...............................................................................................169
81 Generic Module Connector Parasitic Model ............................................................................. 169
82 GVREF Reference Voltage....................................................................................................... 171
83 AGP Layout Guidelines ............................................................................................................ 176
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6300ESB ICH Embedded Platform Design Guide
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M Processor 1.8-V VCCA[3:0] Recommended
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M Processor 1.8 V Intel
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M Processor Socket Core Power Delivery Corridor...................... 92
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M Processor Core Power Delivery
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M Processor Core Power Delivery
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Customer Reference Board
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