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®
Intel
855GME Chipset and Intel
Table 148. Processor Layout Checklist (Sheet 2 of 7)
Checklist Items
IERR#
PROCHOT#
FERR#
THERMTRIP#
IPWRGOOD
®
6300ESB ICH Embedded Platform Design Guide
Recommendations
6300ESB Interface Signals
• May be routed as a test point or to any
optional system receiver.
• May be routed as strip-line or micro-strip with
trace impedance = 55 Ω ± 15%.
• Place series resistor R1 within 3 inches of
system receiver.
• Place pull-up resistor Rtt within 3 inches of
series resistor R1.
• Pull-up voltage for termination resistor Rtt is
VCCP (1.05).
• May be routed as strip-line or micro-strip with
trace impedance = 55 Ω ± 15%.
• Use recommended voltage translation logic
for an appropriate system receiver.
• Pull-up voltage for termination resistor Rtt is
VCCP (1.05)
• Place series resistor Rs at the beginning of
trace T-split and within 3 inches from Q1.
• Connect FERR# to the processor and the
®
Intel
6300ESB.
• Recommend connecting processor signal
THERMTRIP# to the 6300ESB, but may be
connected to any optional system receiver,
with consideration for any voltage level
translation if necessary.
• May be routed as strip-line or micro-strip with
trace impedance = 55 Ω ± 15%.
• Place series resistor R1 within 3 inches of
system receiver.
• Place pull-up resistor Rtt within 3 inches of
series resistor R1.
• Pull-up voltage for termination resistor Rtt is
VCCP (1.05).
• May be routed as strip-line or micro-strip with
trace impedance = 55 Ω ± 15%
• Route point-to-point between an AND gate
output (AND of PWRGD_3V and
CPU_VR_PWRGD) signal and CPU signal
PWRGOOD, trace length range between 0.5
and 12 inches.
• Place a termination resistor Rtt within 3
inches of CPU pin. T-split routing should not
be used.
• Pull-up voltage for termination resistor Rtt is
VCCP (1.05)
January 2007
Layout Checklist
Comments
• Asynchronous AGTL+ Output
Signal.
• Refer to Topology 1A in
Section 4.1.5.1
for resistor values
and trace length
recommendations.
• Asynchronous AGTL+ Output
Signal.
• Refer to Topology 1C in
Section 4.1.5.3
for resistor values
and trace length
recommendations.
• Asynchronous AGTL+ Output
Signals.
• Refer to Topology 1B in
Section 4.1.5.2
for resistor values
and trace length
recommendations.
• Refer to
Section 4.1.5.7
for
voltage translation
recommendations.
• Asynchronous Open Drain CMOS
Input Signal.
• Refer to Topology 2A in
Section 4.1.5.4
for resistor values
and detailed routing
recommendations.
301
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