Table of Contents
Advertisement
®
Intel
855GME Chipset and Intel
®
Intel
Pentium
®
Table 9.
Intel
Pentium
FSB Signal Package Lengths (Sheet 6 of 6)
Signal
Group
Address
Group 2
Host Clocks
ITP Signals
4.1.4
Length Matching Constraints
The routing guidelines presented in the following subsections define the recommended routing
topologies, trace width and spacing geometries, and absolute minimum and maximum routing
lengths for each signal group, which are recommended to achieve optimal SI and timing. In
addition to the absolute length limits provided in the individual guideline tables, there are more
restrictive length matching requirements called length-matching constraints. These additional
requirements further restrict the minimum to maximum length range of each signal group with
respect to clock strobe, within the overall boundaries defined in the guideline tables, as required to
ensure adequate timing margins.
The amount of minimum to maximum length variance allowed for each group around the clock
strobe reference length varies from signal group to signal group depending on the amount of timing
variation that may be tolerated. Refer to
requirements and
®
6300ESB ICH Embedded Platform Design Guide
®
®
M/Celeron
M Processor FSB Design and Power Delivery Guidelines
®
®
M/Celeron
M Processor and GMCH Source Synchronous
®
Intel
Pentium
CPU Signal
M/Celeron
Name
Processor Package
Trace Length (mils)
A31#
773
A30#
773
A29#
773
A28#
773
A27#
773
A26#
773
A25#
773
A24#
773
A23#
773
A22#
773
A21#
773
A20#
773
A19#
773
A18#
773
A17#
773
ADSTB[1]#
773
BCLK0
447
BCLK1
447
BPM[3:0]
593
Table 6
Table 7
for source synchronous address matching requirements.
January 2007
®
®
M
GMCH Signal
Name
HA31#
HA30#
HA29#
HA28#
HA27#
HA26#
HA25#
HA24#
HA23#
HA22#
HA21#
HA20#
HA19#
HA18#
HA17#
HADSTB[1]#
BCLK
BCLK#
—
for source synchronous data matching
GMCH Package Trace
Length (mils)
617
484
558
579
631
556
535
353
382
545
429
414
284
389
457
504
1138
1145
—
55
Advertisement
Table of Contents
