Control Signal Routing Guidelines; Control To Clock Length Matching Requirements - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
System Memory Design Guidelines (DDR-SDRAM)
5.4.5.2

Control Signal Routing Guidelines

Table 36
Table 36. Control Signal Routing Guidelines
Signal Group
Motherboard Topology
Reference Plane
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Minimum Spacing to Trace Width Ratio
Minimum Isolation Spacing to non-DDR Signals
Package Length P1
Trace Length P1 + L1 – GMCH Die-Pad to DIMM Pad
Trace Length L2 – DIMM Pad to Parallel Termination
Resistor Pad
Parallel Termination Resistor (Rt)
Maximum Recommended Motherboard Via Count
Per Signal
Length Matching Requirements
NOTES:
1. Recommended resistor values and trace lengths may change in a later revision of the design guide.
2. Power distribution vias from Rt to Vtt are not included in this count.
3. It is possible to route using two vias if one via is shared that connects to the DIMM pad and parallel
termination resistor.
4. The overall maximum and minimum length to the DIMM must comply with clock length matching
requirements.
5.4.5.3

Control to Clock Length Matching Requirements

The length of the control signals, between the GMCH die-pad and the DIMM must fall within the
range defined below, with respect to the associated clock reference length. Refer to
definition of the various trace segments that make up this path. The length of trace from the DIMM
to the termination resistor need not be length matched. The length matching requirements are also
shown in
X = SCK[2:0]/SCK[2:0]# total reference length, including package length. Refer to
0
Section 5.4.3.1
Y = SCS[1:0]# and SCKE[1:0] total length = GMCH package length + L1, as shown in
0
where:
– 1.5") ≤ Y
(X
0
140
®
6300ESB ICH Embedded Platform Design Guide
defines the control signal routing guidelines.
Parameter
Figure 70. Length range formula for DIMM0:
for more information.
≤ (X
- 0.5")
0 0
Routing Guidelines
SCKE[3:0], SCS[3:0]#
Point-to-Point with Parallel Termination
Ground Referenced
55 Ω ± 15%
Inner layers: 4 mils
Outer layers: 5 mils
2:1 (e.g., 8 mil space to 4 mil trace)
20 mils
500 mils ± 250 mils
Refer to package length for exact lengths.
Min = 2.0 inches
Max = 6.0 inches
Max = 2.0 inches
56 Ω ± 5%
3
Match CTRL to SCK[5:0]/SCK[5:0]#
Refer to length matching in Section 5.4.5.3
Figure 70.
and
Figure 69 for a
Figure 69,