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®
Intel
855GME Chipset and Intel
Figure 132.
FWH/CPU UP Signal Topology Solution
NOTE: The recommended value for R1 depends on the Processor used in the system. See the Processor
design guidelines for more info.
.
Figure 133.
FWH Level Translation Circuitry
From_Driver
Note: This transition circuit is optimized to function with the low voltage processors the
9.13.5
FWH V
The V
pin on the FWH is used for programming the flash cells. The FWH supports V
PP
or 12 V. When V
FWH only supports 12 V V
The 12 V V
occurs very infrequently (much less than 80 hours). The V
motherboard. (See
V
CPU
CC
Processor
R1
L1
Ω
2 K
± 5%
3904
Ω
300
± 5%
ICH supports.
Design Guidelines
PP
is 12 V, the flash cells programs about 50% faster than at 3.3 V. However, the
PP
for 80 hours (3.3 V on Vpp does not affect the life of the device).
PP
would be useful in a programmer environment, which is typically an event that
PP
Figure
134.)
January 2007
®
6300ESB ICH Embedded Platform Design Guide
®
Intel
®
Intel
6300ESB
I/O Controller
Hub
L2
L3
V
_of_Receiver
CC
T1
3904
T1 = 10" max
T2 = 3" max
pin MUST be tied to 3.3 V on the
PP
6300ESB Design Guidelines
FWH
Voltage
Translator
B1187-02
Ω
300
± 5%
T2
To_Receiver
®
Intel
6300ESB
B1190-02
of 3.3 V
PP
241
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