Ddr Clock Routing Guidelines; Table 44. Clock Signal Group Routing Guidelines - Intel 855GM Design Manual

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7.3.3.

DDR Clock Routing Guidelines

Table 44. Clock Signal Group Routing Guidelines

Signal Group
Topology
Reference Plane
Single Ended Trace Impedance ( Zo )
Differential Mode Impedance (Zdiff)
Nominal Trace Width
(see exceptions for breakout region below)
Nominal Pair Spacing (edge to edge)
(see exceptions for breakout region below)
Minimum Pair to Pair Spacing
(see exceptions for breakout region below)
Minimum Serpentine Spacing
Minimum Spacing to Other DDR Signals
(see exceptions for breakout region below)
Minimum Isolation Spacing to non-DDR Signals
Maximum Via Count
Package Length Range – P1
L1
L2
L3
L4
L5
Total Length
SCK to SCK# Length Matching
Clock to Clock Length Matching (Total Length)
®
Intel 855GM/855GME Chipset Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration
Parameter Definition
SCK[5:0] and SCK#[5:0]
Differential Pair Point to Point
Ground Referenced
42 ohms +/-15%
70 ohms +/- 15%
Inner Layers: 7 mils
Outer Layers: 8 mils (pin escapes only)
Inner Layers: 4 mils
Outer Layers: 5 mils (pin escapes only)
20 mils
20 mils
20 mils
25 mils
2 (per side Micro-Dimm) 5 (per side Memory Down)
1000 mils +/- 350mils
(See clock package length Table 45 for exact lengths.)
Max = 300 mils (breakout segment)
Min = 0.25 inches
Max = 4.5 inches
Max = .5" inches (see Figure 54)
Min = 0.25 in. Max = 1.0 in. (See Figure 55, Figure 56 and Figure
57)
Max = 0.5 inches (see Figure 55 and Figure 57)
Max = 0.25 inches (see Figure 56)
Max = 0.25 inches
Total length target is determined by placement (see Figure 54,
Figure 55, Figure 56 and Figure 57)
Total length for Micro-DIMM group = X0 (see Figure 58)
Total length for Memory Down group = X1 (see Figure 58)
Match total length to +/- 10 mils (see Section 7.3.3.1)
Match all Micro-DIMM clocks to X0 +/- 25 mils (see section
7.3.3.2)
Match all Memory Down clocks to X1 +/- 25 mils (see section
7.3.3.2)
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