Intel ® 6300Esb Design Guidelines; Serial Ata Interface; Layout Guidelines; General Routing And Placement - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
®
Intel 6300ESB Design Guidelines
9.1

Serial ATA Interface

9.1.1

Layout Guidelines

Note: These routing guidelines are created using the stack-ups described in
Stack-Up" on page
9.1.1.1

General Routing and Placement

Use the following general routing and placement guidelines when laying out a new design.
4. Serial ATA signals must be have consistent plane re ferencing maintained for the entire path
between driver and receiver. Signals routed on microstrip may be referenced to either power or
ground but not both. Stripline signals should be surrounded by power planes (Vcc or GND)
and shall be maintained consistent along the entire transmission path.
5. Route all traces using microstrip over continuous planes (Vcc or GND), with no interruptions.
Avoid crossing over anti-etch if at all possible. Any discontinuity or split in the ground plane
may cause signal reflections and should be avoided.
6. No layer changes or vias other than the package ball shall be allowed.
7. Do not route SATA traces around or under crystals, oscillators, clock synthesizers, magnetic
devices or ICs that use and/or duplicate clocks.
8. No 90 degree bends or stubs.
9. The allowable breakout region is 500 mils from the package.
10. Do not route SATA traces through connectors or any other obstruction that would require a
deviation in the intra-pair spacing and thus, differential impedance. The exception is the
breakout region from the pin whose length should be minimized to reduce reflections.
9.1.1.2

Serial ATA Trace Separation

Use the following separation guidelines.
trace spacing.
1. Maintain parallelism and consistent trace spacing between SATA differential signals with the
trace spacing needed to achieve 79.3 Ω ± 10% differential impedance. Deviations will
normally occur due to package breakout and routing to connector pins. Ensure that the amount
and length of the deviations are kept to the minimum possible.
2. Use an impedance calculator to determine the trace width and spacing required for the specific
board stackup being used; keeping in mind that the target is a 79.3 Ω ± 10% differential
impedance. For the board stackup parameters referred to in
Stack-Up" on page
10% differential trace impedance.
3. Based on simulation data, use 100 mil minimum spacing between 6300ESB Serial ATA signal
pairs and other signal traces for optimal signal quality. This helps to reduce crosstalk.
®
6300ESB ICH Embedded Platform Design Guide
33.
Figure 92
33, 7.0 mil traces with 6.0 mil spacing results in approximately 79.3 Ω ±
January 2007
®
Intel 6300ESB Design Guidelines
Section 3.1, "Nominal Board
provides an illustration of the recommended
Section 3.1, "Nominal Board
9
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