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Summary of Contents for Intel 6300ESB ICH
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® Intel Xeon™ Processor with 800 ® MHz System Bus, Intel E7520 ® Chipset, and Intel 6300ESB ICH Development Kit User’s Manual September 2004 Reference Number: 300281-003...
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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Changed figures that referenced PCI-X to PCI-X 133 MHz; changed jumpers on Figure 4; made other miscellaneous changes. Changed code names to public names; clarified illustrations. Initial release of this document. ® ® E7520 Chipset, Intel 6300ESB ICH Development Kit User’s Manual Description...
6300ESB ICH Development Kit comprise an IA-32 based dual-processor platform. This platform serves as a reference for OEMs development platform. This and other development kits from Intel provide a fully working product with range of performance options which can be modified or used immediately for product development.
— One PCI Express x8 slot — One PCI Express x4 slot — One 5 V PCI-32/33 slot connected through the Intel — Two 3.3 V PCI-X 64/66 slots connected through the Intel • Low Pin Count Bus — National* LPC 47M172 Super I/O residing on LPC bus —...
Intel system bus and Intel Block Diagram ® Figure 1. Intel Xeon™ Processor with 800 MHz System Bus and Intel 6300ESB Customer Reference Board Block Diagram PCI-X 133 MHz P CI-X 100MHz ® ®...
Memory Subsystem The memory subsystem is designed to support Double Data Rate2(DDR2) Synchronous Dynamic Random Access Memory (SDRAM) using the Intel(R) E7520 MCH. The MCH provides two independent DDR channels, which support DDR2 400 DIMMs. The peak bandwidth of each DDR2 branch channel is 3.2 Gbyte/s (8 bytes x 400 MT/s) with DDR2 400.
DIMMs are used. This recommendation is based on the signal integrity requirements of the DDR2 interface. Figure 3. DDR2 400 Memory - DIMM Ordering ® Intel Xeon™ Processor, Intel ® ® E7520 Chipset, Intel 6300ESB ICH Development Kit User’s Manual 3519-01...
Halt and Stop Clock (processor C1 and C2 states). S0 affords the fastest wake-up response time of any sleep state because the system remains fully powered and memory is intact. ® ® Intel Xeon™ Processor, Intel E7520 Chipset, Intel Platform Management ® 6300ESB ICH Development Kit User’s Manual...
Although the system must power up and fully boot, boot time to an application is reduced because the platform is returned to the same system state as when the preceding power off occurred. ® Intel Xeon™ Processor, Intel ® ® E7520 Chipset, Intel 6300ESB ICH Development Kit User’s Manual...
The LM 93 monitors the majority of the system voltages. The VID signals from the processors are also monitored by LM 93. All voltage levels can be read via the SMBus. ® ® Intel Xeon™ Processor, Intel E7520 Chipset, Intel Platform Management ® 6300ESB ICH Development Kit User’s Manual...
Monitor • PS/2 mouse and keyboard Visually inspect the board and ensure that the MCH, Intel other components did not shake loose during shipment. If the board has any loose or missing components, contact your Intel representative. Caution: Powering up without all components installed correctly could lead to a power-up failure that could damage the board.
Equipment Required for CRB Usage Driver and OS Requirements The required INF driver for the CRB supports the functionality of the Intel Controller and PXH. The INF file will be included with Red Hat compatible drivers on the CD shipped with the kit.
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& ich5 southbridges patches/ide-sata/ide_pci-hr-ich5.patch integrated into the esb6300 & ich5 southbridges patches/ide-sata/pci_irq-hr.patch integrated into the esb6300 & ich5 southbridges ® ® ® Intel Xeon™ Processor, Intel E7520 Chipset, Intel 6300ESB ICH Development Kit User’s Manual...
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Intel INF update utility 3.2.1.4 Third Party Drivers Included on the CD is software compatible with the ATI Rage* Mobility-M Graphics Accelerator 021112a-006561C-ATI.zip. ® Intel Xeon™ Processor, Intel ® ® E7520 Chipset, Intel 6300ESB ICH Development Kit User’s Manual...
1-2: Enable 3.3 V AUX for wake events Open: 3.3 V Operation Only Enable PXH J2G2 1-2: Enable Open: Disable Prevents the system from rebooting following a reset from Intel 6300ESB I/O Controller J2G3 1-2: No Reboot Open: Normal Enable on SIO J2J1 1-2: Enable...
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Intel 6300ESB I/O Controller Top Swap 1-2: Top Swap J5F1 Open: Normal See MCH Documentation for alternative Gear J5F113 Ratios for MCH FSB/Memory ® 6300ESB ICH Development Kit User’s Manual Jumpers and Headers Default Position SPEED Normal RSVD BSEL0: 1-2...
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Manual VID select J9K1 1-2: Manual select Open: CPU select 1-2: VID[5] 3-4: VID[4] 5-6: VID[3] J9K2 7-8: VID[2] 9-10: VID[1] 11-12: VID[0] ® ® E7520 Chipset, Intel 6300ESB ICH Development Kit User’s Manual Default Position Open Open Open Open Open Required...
Power Diagrams Figure 5 shows the power distribution for the CRB. Refer to the CRB schematics for details on the power distribution logic. (Contact your Intel field sales representative to obtain the schematics file.) Figure 5. Power Distribution Block Diagram 12 V 5.0 V...
Platform Resets Figure 7 depicts the reset logic for the CRB. The Intel 6300ESB I/O Controller provides most of the reset following assertion of power good and system reset. However, the glue logic within the SIO is also used to buffer reset to PXH, MCH, FWH, and IDE.
Express bus. The PXH uses PAIRQ for the Channel A interface to PCI-X 64-bit/100 MHz peripherals and PBIRQ for the Channel B interface to PCI-X 64/133. MSI and Non Maskable Interrupt (NMI) are connected from the Intel 6300ESB I/O Controller to CPU0 and CPU1. The platform also supports MSI for maskable and non-maskable interrupts.
Debug Procedure The debug procedures in this section are used to determine baseline functionality for the Intel Xeon™ Processor with 800 MHz System Bus, Intel Development Kit. This is a cursory set of tests designed to provide a level of confidence in the platform operation.
R6F2: 0.775 V Vref incorrect: check resistor values R3M1: 0.9 V Vref incorrect: check resistor values R2M1: 0.9 V Vref incorrect: check resistor values ® ® E7520 Chipset, Intel 6300ESB ICH Development Kit User’s Manual Cause of Failure Cause of Failure...
Inserting Processor in Socket 2. Clean the processor’s top surface with a clean towel and isopropyl alcohol. (See Figure 13. Cleaning the Processor Surface ® Intel Xeon™ Processor, Intel ® ® E7520 Chipset, Intel 6300ESB ICH Development Kit User’s Manual Figure 13.)
5. Place the heat sink on top of the CPU and align the four screws to the threads of the backplate. ® ® Intel Xeon™ Processor, Intel E7520 Chipset, Intel Figure 15.) ® 6300ESB ICH Development Kit User’s Manual Heatsink Assembly Figure 14.) Remove plastic...
7. Plug the fan connector into the nearest fan connector on the PCB. 8. If applicable, repeat this process for the second processor. ® Intel Xeon™ Processor, Intel ® ® E7520 Chipset, Intel 6300ESB ICH Development Kit User’s Manual Tighten screw 4 Tighten screw 2 Figure 16. The...