Ddr Clock Routing Guidelines; Table 33. Clock Signal Group Routing Guidelines - Intel 852GM Design Manual

System Memory Design Guidelines (DDR-SDRAM)
7.3.3.

DDR Clock Routing Guidelines

Table 33. Clock Signal Group Routing Guidelines

Signal Group
Topology
Reference Plane
Single Ended Trace Impedance ( Zo )
Differential Mode Impedance (Zdiff)
Nominal Trace Width
(see exceptions for breakout region below)
Nominal Pair Spacing (edge to edge)
(see exceptions for breakout region below)
Minimum Pair to Pair Spacing
(see exceptions for breakout region below)
Minimum Serpentine Spacing
Minimum Spacing to Other DDR Signals
(see exceptions for breakout region below)
Minimum Isolation Spacing to non-DDR Signals
Maximum Via Count
Package Length Range – P1
Trace Length Limits – L1
Total MB Length Limits – L1 + L2
Total Length – P1 + L1 + L2
SCLK to SCLK# Length Matching
Clock to Clock Length Matching (Total Length)
Breakout Exceptions
(Reduced geometries for GMCH breakout region)
NOTES:
1. Pad-to-Pin length tuning is utilized on clocks in order to achieve minimal variance. Package lengths range
between approximately 600 mils and 1400 mils. Exact package lengths for each clock signal are provided at
the end of this Section. Overall target length should be established based on placement and routing flow. The
resulting motherboard segment lengths must fall within the ranges specified.
2. The DDR clocks should be routed on internal layers, except for pin escapes. It is recommended that pin escape
vias be located directly adjacent to the ball pads on all clocks. Surface layer routing should be minimized.
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Parameter Definition
SCK[4,3,1,0] and SCK#[4,3,1,0]
Differential Pair Point to Point
Ground Referenced
42 ohms ± 15%
70 ohms ± 15%
Inner Layers: 7 mils
Outer Layers: 8 mils (pin escapes only)
Inner Layers: 4 mils
Outer Layers: 5 mils (pin escapes only)
20 mils
20 mils
20 mils
25 mils
2 (per side)
1000 mils ± 350 mils
(See clock package length Table 34 for exact lengths.)
Max = 300 mils (breakout segment)
Min = 0.5"
Max = 5.0"
Total length target is determined by placement (see Figure 43)
Total length for SO-DIMM0 group = X0 (see Figure 44)
Total length for SO-DIMM1 group = X1 (see Figure 44)
Match total length to ±10 mils (see Section 7.3.3.1)
Match all SO-DIMM0 clocks to X0 ± 25 mils (see Figure 44)
Match all SO-DIMM1 clocks to X1 ± 25 mils (see Figure 44)
Inner Layers: 4 mil trace, 4 mil pair space allowed
Outer Layers: 5 mil trace, 5 mil pair space allowed
Pair to pair spacing of 5 mils allowed
Spacing to other DDR signals of 5 mils allowed
Maximum breakout length is 0.3"
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Intel 852GM Chipset Platform Design Guide
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