Intel 855GME Design Manual page 306

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Intel 855GME Chipset and Intel
Layout Checklist
Table 148. Processor Layout Checklist (Sheet 7 of 7)
Checklist Items
VCC (CORE)
Decoupling
VCCP
Decoupling
NOTES:
1. A[31:3]# pins on the processor correspond to HA[31:3]# pins on the GMCH.
2. ADSTB[1:0]# pins on the processor correspond to HADSTB[1:0]# pins on the GMCH.
3. DSTBN[3:0]# pins on the processor correspond to HDSTBN[3:0]# pins on the GMCH.
4. DSTBP[3:0]# pins on the processor correspond to HDSTBP[3:0]# pins on the GMCH.
5. D[63:0]# pins on the processor correspond to HD[63:0]# pins on the GMCH.
6. REQ[4:0]# pins on the processor correspond to HREQ[4:0]# pins on the GMCH.
7. The RESET# pin on the processor corresponds to the CPURST# pin on the GMCH. Refer to the ITP
portion of this checklist,
ITP700FLEX debug port.
8. The TRDY# pin on the processor corresponds to the HTRDY# pin on the GMCH.
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6300ESB ICH Embedded Platform Design Guide
Recommendations
• Recommended bulk decoupling:
• (4) 220 µF SP caps - ESR 12 m Ω (max) and
ESL 3.5 µH, placed near CPU north power
corridor (pin map row AF).
• Recommended mid-frequency decoupling:
• (35) 10 µF 0805 caps - ESR 5 m Ω (typ) and
ESL 0.6 nH placed in and near package
outline.
• Sharing of vias between several VCC-CORE
pins or ground pins is not allowed.
• Recommended bulk decoupling:
• (2) 150 µF POSCAP - ESR 42 m Ω (typ) and
ESL 2.5 nH, placed one each near the CPU
and the GMCH packages.
• (10) 0.1 µF X7R 0603 caps - ESR 16 m Ω
(typ) and ESL 0.6 nH, placed on the
secondary side within the CPU package
outline.
Section 4.1.6 and Section 4.3.1.1
Comments
• It is highly recommended that
decoupling guidelines detailed in
Section 4.4.3 be followed for
efficient VRM performance.
• Refer to Section 4.4.4
processor VCCP decoupling
recommendations.
for treatment of RESET# when using
for