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®
Intel
855GME Chipset and Intel
4.8.10
6300ESB Power Signal Decoupling
Table 26.
Power Signal Decoupling
V_CPU_IO
V
RTC
CC
V
3.3
CC
V
Sus3.3
CC
V
1_5
CC
V
Sus1_5
CC
V5REF_Sus
V5REF
V
PLL
CC
V
HI
CC
VCCREF (3.3 V)
VCCA
4.8.11
Hub Interface Decoupling
Refer to
Section 8.1.6
4.8.12
FWH Decoupling
A 0.1 µF capacitor shall be placed between the VCC supply pins and the VSS ground pins to
decouple high-frequency noise, which may affect the programmability of the device. Additionally,
a 4.7
F capacitor should be placed between the V
µ
decouple low frequency noise. The capacitors should be placed no further than 390 mils from the
V
supply pins. Note that the value of the low-frequency bulk decoupling capacitor is dependent
CC
on board layout and system power supply design.
4.9
Thermal Design Power
Refer to the Intel
Embedded Applications and the Intel
Design Guide for information on thermal design.
Pin
Capacitor
0.1 µF
0.1 µF
0.1 µF
0.01µF
0.1 µF
0.01 µF
1.0 µF
0.1 µF
0.01 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
1.0 µF
0.1 µF
for details.
®
855GME Chipset Memory Controller Hub (MCH) Thermal Design Guide for
January 2007
®
6300ESB ICH Embedded Platform Design Guide
Quantity
1
2
12
4
4
1
1
6
2
4
1
1
3
2
1
1
supply pins and the V
CC
®
6300ESB I/O Controller Hub Thermal and Mechanical
Decoupling Placement
Close to the 6300ESB
One close to the 6300ESB and
one close to the battery
Close to the 6300ESB
ground pins to
SS
121
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