Watchdog Timer Mode Register (Wdtm); Noise Elimination - NEC V850/SA1 mPD703015 Preliminary User's Manual

5.3.7 Watchdog timer mode register (WDTM)

Read/write is available in 8- or 1-bit units.
Figure 5-12. Watchdog Timer Mode Register (WDTM) Format
After reset: 00H R/W
Symbol 7
WDTM RUN
RUN
0 Count operation stop
1 Count start after clearing
WDTM4
0 Interval timer mode
1 WDT mode
Caution If 1 is set to RUN or WDTM4 bit, no operation other than the reset input is available for clearing
this register.

5.3.8 Noise elimination

(1) Noise elimination of INTP0 to INTP3 pins
NMI and INTP0 to INTP3 pins incorporate the noise elimination circuit by means of the analog delay. Unless an
input level to each pin is maintained more than a certain interval, the input pulse cannot be detected as an edge.
The edge is detected in a certain interval.
(2) Noise elimination of INTP4 to INTP6 pins
INTP4 to INTP6 pins incorporate the digital noise elimination circuit. If an input level of the INTP pin is detected
with the sampling clock (f
nated as a noise. Note the followings:
• In the case that the input pulse width is between 2 and 3 clocks, whether the input pulse is detected as a
valid edge or eliminated as a noise is indefinite.
• To securely detect the level as a pulse, the same level input of 3 x 1/ f
• When the noise generates in synchronous with a sampling clock, this may not be recognized as a noise. In
this case, eliminate the noise with an addition of a filter to the input pin.
120
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Address: FFFFF384H
6 5 4
0 0 WDTM4
Watchdog Timer Operation Control
Timer Mode Selection/Interrupt Control by WDT
) and the same level is not detected three successive times, the input pulse is elimi-
xx
3 2 1
0 0 0
or more is required.
xx
0
0