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HALT Mode Setting
Item
External bus interface
External
NMI
interrupt
INTP0 to INTP3
request
INTP4 to INTP6
During
AD0 to AD15
external
A16 to A21
expansion
LBEN, UBEN
mode
R/W
DSTB, WRL,
WRH, RD
ASTB
HLDAK
Note Even when the HALT instruction has been executed, the instruction fetch operation continues until the
on-chip instruction prefetch queue becomes full. Once it is full, operation stops according to the status
shown in the Table 6-1.
(2) Cancellation of HALT mode
HALT mode can be canceled by an NMI request, an unmasked maskable interrupt request, and input to the
RESET pin.
(a) Cancellation by interrupt request
HALT mode is canceled regardless of the priority level when an NMI request or an unmasked maskable
interrupt request occurs. However, the following occurs if HALT mode was set as part of an interrupt
servicing routine.
(i)
Only HALT mode is canceled when an interrupt request that has a lower priority level than the interrupt
currently being serviced occurs, and the lower-priority interrupt request is not acknowledged. The
interrupt request itself is retained.
(ii) When an interrupt request (including NMI request) that has a higher priority level than the interrupt
currently being serviced occurs, HALT mode is canceled and the interrupt request is acknowledged.
(b) Cancellation by RESET pin input
This is the same as for normal reset operations.
138
CHAPTER 6
CLOCK GENERATION FUNCTION
Table 6-1. Operating Statuses during HALT Mode (2/2)
When CPU Operates via Main Clock
When sub clock does
When sub clock exist
not exist
Only bus hold function operates
Operating
Operating
Operating
Note
High impedance
Note
Hold
(high impedance when HLDAK = 0)
Note
High level output
(high impedance when HLDAK = 0)
Operating
When CPU Operates via Sub Clock
When main clock's
When main clock's
oscillation continues
oscillation is stopped
Stopped
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