Table of Contents
Advertisement
Figure 7-2. Format of 16-Bit Timer Mode Control Register 0, 1 (TMC0, TMC1) (2/2)
OVFn
0
Overflows.
1
Does not overflow.
Cautions 1. Write operation to bits other than OVFn flag must be performed after halting the timer
operation.
2. The valid edge of the TIn0 pin is selected by using the prescaler mode register n (PRMn).
3. When a mode in which the timer is cleared and started on coincidence between TMn and
CRn0, the OVFn flag is set to 1 when the count value of TMn changes from FFFFH to 0000H
with CRn0 set to FFFFH.
Remark
TOn
: Output pin of timer n
TIn0
: Input pin of timer n
TMn
: 16-bit timer register n
CRn0 : Compare register n0
CRn1 : Compare register n1
152
CHAPTER 7
TIMER/COUNTER FUNCTION
Detection of Overflow of 16-bit Timer Register n
Advertisement
Table of Contents
