Format Of Iic Status Register (Iics0) - NEC V850/SA1 mPD703015 Preliminary User's Manual

(2) IIC status register (IICS0)
This register indicates the status of the I
IICS0 can be set by a 1-bit or 8-bit memory manipulation instruction. IICS0 is a read-only register.
RESET input sets IICS0 to 00H.
After reset : 00H R
7 6
IICS0 MSTS ALD
MSTS
0 Slave device status or communication standby status
1 Master device communication status
Condition for clearing (MSTS = 0)
• When a stop condition is detected
• When ALD = 1
• Cleared by LREL = 1
• When IICE changes from 1 to 0
• When RESET is input
ALD
0 This status means either that there was no arbitration or that the arbitration result was a "win".
1 This status indicates the arbitration result was a "loss". MSTS is cleared.
Condition for clearing (ALD = 0)
• Automatically cleared after IICS0 is read
• When IICE changes from 1 to 0
• When RESET is input
Note This register is also cleared when a bit manipulation instruction is executed for bits other than IICS0.
Remark LREL : Bit 6 of IIC control register (IICC0)
IICE : Bit 7 of IIC control register (IICC0)
CHAPTER 10 SERIAL INTERFACE FUNCTION
2
C bus.
Figure 10-10. Format of IIC Status Register (IICS0) (1/3)
Address: FFFFF342H
5 4
EXC COI
Note
3 2 1
TRC ACKD STD
Master Device Status
Condition for setting (MSTS = 1)
• When a start condition is generated
Detection of Arbitration Loss
Condition for setting (ALD = 1)
• When the arbitration result is a "loss".
0
SPD
227