Priority Control; Priorities Of Interrupts And Exceptions; Multiple Interrupt Processing - NEC V850/SA1 mPD703015 Preliminary User's Manual

5.6 Priority Control

5.6.1 Priorities of interrupts and exceptions

RESET
RESET
×
NMI
×
INT
×
TRAP
×
ILGOP
RESET : reset
NMI : non-maskable interrupt
INT : maskable interrupt
TRAP : software exception
ILGOP : illegal op code exception
* : Item on the left ignores the item above.
×
: Item on the left is ignored by the item above.
↑
: Item above is higher than the item on the left in priority.
←
: Item on the left is higher than the item above in priority.

5.6.2 Multiple interrupt processing

Multiple interrupt processing is a function which allows the nesting of interrupts. If a higher priority interrupt is
generated and accepted, it will be allowed to stop a current interrupt service routine in progress. Execution of the
original routine will resume once the higher priority interrupt routine is completed.
If an interrupt with a lower or equal priority is generated and a service routine is currently in progress, the later in-
terrupt will be pended.
Multiple interrupt processing control is performed when it is in the state of interrupt acceptance (ID = 0). Even in
an interrupt processing routine, this control must be set in the state of acceptance (ID = 0). If a maskable interrupt
acceptance or exception is generated during a service program of maskable interrupt or exception, EIPC and EIPSW
must be saved.
The following example shows the procedure of interrupt nesting.
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
NMI INT TRAP
* *
←
↑
↑ ↑
↑ ↑
ILGOP
* *
← ←
← ←
←
↑
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