Page 1 User’s Manual µ PD178054 Subseries 8-Bit Single-Chip Microcontrollers µ PD178053 µ PD178054 µ PD178F054 Document No. U15104EJ2V0UD00 (2nd edition) Date Published January 2002 N CP(K) © 2001 Printed in Japan...
Page 2 [MEMO] User’s Manual U15104EJ2V0UD...
Page 3 Reset operation must be executed immediately after power-on for devices having reset function. FIP and IEBus are trademarks of NEC Corporation. Windows and WindowsNT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 4 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 Major Revisions in This Edition Page Description Change of µ PD178053, 178054, and 178F054 status from under development to development completed Throughout pp.8, 9 Modification of Related Documents p.25 Modification of 1.5 Development of 8-Bit DTS Series p.55 Modification of bit units for manipulation for OSTS in Table 3-4 Special Function Registers p.84 Deletion of pins P10 to P15 from Table 4-3 Port Mode Register and Output Latch Settings When Using Alternate Functions...
Page 7 PREFACE Readers This manual has been prepared for user engineers who wish to understand the functions of the µ PD178054 Subseries and design and develop its application systems and programs. Purpose This manual is intended to give users an understanding of the functions described in the Organization below.
Page 8 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. µ PD178054 Subseries User’s Manual This manual 78K/0 Series Instruction User’s Manual U12326E 78K/0 Series Application Note Basics (I)
Page 9 Document No. SEMICONDUCTOR SELECTION GUIDE -Products & Packages- X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The related documents listed above are subject to change without notice.
Page 10: Table Of Contents
TABLE OF CONTENTS CHAPTER 1 OUTLINE ........................Features..........................Applications ........................Ordering Information ......................Pin Configuration (Top View) ..................Development of 8-Bit DTS Series ................... Block Diagram ........................Functional Outline ......................CHAPTER 2 PIN FUNCTION ......................Pin Function List ....................... Description of Pin Functions ..................2.2.1 P00 to P06 (Port 0) ......................
Page 11 Processor Registers ......................3.2.1 Control registers ........................3.2.2 General-purpose registers ....................3.2.3 Special Function Registers (SFR) ..................Instruction Address Addressing ..................3.3.1 Relative addressing ......................3.3.2 Immediate addressing ......................3.3.3 Table indirect addressing ..................... 3.3.4 Register addressing ......................Operand Address Addressing ..................3.4.1 Implied addressing .......................
Page 12 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 ............. Functions of 8-Bit Timer/Event Counters 50 to 53 ............Configuration of 8-Bit Timer/Event Counters 50 to 53 ..........Registers Controlling 8-Bit Timer/Event Counters 50 to 53 ........101 Operations of 8-Bit Timer/Event Counters 50 to 53 ............. 105 6.4.1 Operation as interval timer (8-bit) ..................
Page 13 CHAPTER 12 INTERRUPT FUNCTIONS ..................156 12.1 Interrupt Function Types ....................156 12.2 Interrupt Sources and Configuration ................156 12.3 Registers Controlling Interrupt Functions ..............160 12.4 Interrupt Servicing Operations ..................166 12.4.1 Non-maskable interrupt request acknowledgement operation ........... 12.4.2 Maskable interrupt request acknowledgement operation ...........
Page 14 CHAPTER 18 INSTRUCTION SET ....................226 18.1 Conventions ........................227 18.1.1 Operand symbols and description ..................18.1.2 Description of “operation” column ..................18.1.3 Description of “flag operation” column ................18.2 Operation List ........................229 18.3 Instructions Listed by Addressing Type ............... 237 CHAPTER 19 ELECTRICAL SPECIFICATIONS ................
Page 15 LIST OF FIGURES (1/4) Figure No. Title Page Pin I/O Circuits ............................ Memory Map of µ PD178053 ......................Memory Map of µ PD178054 ......................Memory Map of µ PD178F054 ......................Data Memory Addressing of µ PD178053 ..................Data Memory Addressing of µ PD178054 ..................Data Memory Addressing of µ...
Page 16 LIST OF FIGURES (2/4) Figure No. Title Page Block Diagram of 8-Bit Timer/Event Counter 50 ................Block Diagram of 8-Bit Timer/Event Counter 51 ................Block Diagram of 8-Bit Timer/Event Counter 52 ................Block Diagram of 8-Bit Timer 53 ......................Format of Timer Clock Select Registers 50 to 52 (TCL50 to TCL52) ..........Format of Timer Clock Select Register 53 (TCL53) ................
Page 17 LIST OF FIGURES (3/4) Figure No. Title Page 11-1 Block Diagram of Serial Interface SIO30 ................... 11-2 Block Diagram of Serial Interface SIO31 ................... 11-3 Block Diagram of Serial Interface SIO32 ................... 11-4 Format of Serial Operating Mode Registers 30 to 32 (CSIM30 to CSIM32) ........11-5 Format of Serial Port Select Register 32 (SIO32SEL) ..............
Page 18 LIST OF FIGURES (4/4) Figure No. Title Page 15-1 Format of Oscillation Stabilization Time Select Register (OSTS) ............ 15-2 HALT Mode Release upon Interrupt Generation ................15-3 HALT Mode Release by RESET Input ....................15-4 STOP Mode Release by Interrupt Request Generation ..............15-5 Release by STOP Mode RESET Input ....................
Page 19 LIST OF TABLES (1/2) Table No. Title Page Pin I/O Circuit Type and Recommended Connections of Unused Pins ........... Internal Memory Capacities ........................ Vector Table ............................Absolute Address of General-Purpose Registers ................Special Function Registers ......................... Port Functions ............................. Port Configuration ..........................Port Mode Register and Output Latch Settings When Using Alternate Functions ......
Page 20 LIST OF TABLES (2/2) Table No. Title Page 16-1 Hardware Status After Reset ......................Differences Between µ PD178F054 and Mask ROM Versions ............17-1 17-2 Set Value of Memory Size Switching Register .................. 17-3 Set Value of Internal Expansion RAM Size Switching Register ............17-4 Communication Modes ........................
Page 21: Chapter 1 Outline
CHAPTER 1 OUTLINE 1.1 Features • Internal ROM and RAM Item Program Memory Data Memory Part Number Internal High-Speed RAM µ PD178053 24 KB 1024 bytes µ PD178054 32 KB µ PD178F054 Flash memory 32 KB • Instruction set suitable for system control •...
Page 22: Applications
CHAPTER 1 OUTLINE 1.2 Applications Car stereos 1.3 Ordering Information Part Number Package µ PD178053GC-×××-8BT 80-pin plastic QFP (14 × 14) µ PD178054GC-×××-8BT 80-pin plastic QFP (14 × 14) µ PD178F054GC-8BT 80-pin plastic QFP (14 × 14) Remark ××× indicates ROM code suffix. User’s Manual U15104EJ2V0UD...
Page 23: Pin Configuration (Top View)
CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) • 80-pin plastic QFP (14 × 14) µ PD178053GC-×××-8BT, 178054GC-×××-8BT, 178F054GC-8BT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P10/ANI0 P37/BUZ P11/ANI1 P36/BEEP0...
Page 24 CHAPTER 1 OUTLINE Pin Name AMIFC: AM intermediate frequency counter input P130 to P132: Port 13 ANI0 to ANI5: A/D converter input REGCPU: Regulator for CPU power supply BEEP0, BUZ: Buzzer output REGOSC: Regulator for oscillator EO0, EO1: Error out output RESET: Reset input FMIFC:...
Page 25: Development Of 8-Bit Dts Series
CHAPTER 1 OUTLINE 1.5 Development of 8-Bit DTS Series Products in mass production Products under development Flash memory version Mask ROM version or PROM version µ µ 80 pins PD178048 Subseries PD178F048 80 pins On-chip OSD controller On-chip OSD controller 8-bit PWM ×...
Page 26: Block Diagram
CHAPTER 1 OUTLINE 1.6 Block Diagram TI50/P33 8-bit timer/ P00 to P06 Port 0 event counter50 TO50/P130 TI51/P34 8-bit timer/ P10 to P15 Port 1 event counter51 TO51/P131 TI52/P77 8-bit timer/ P30 to P37 Port 3 event counter52 TO52/P132 78K/0 8-bit timer53 Flash Port 4...
Page 27: Functional Outline
CHAPTER 1 OUTLINE 1.7 Functional Outline µ PD178053 µ PD178054 µ PD178F054 Item Internal 24 KB 32 KB 32 KB (Mask ROM) (Mask ROM) (Flash memory) High-speed RAM 1024 bytes 8 bits × 32 registers (8 bits × 8 registers × 4 banks) General-purpose registers 0.45 µ...
Page 28: Chapter 2 Pin Function
CHAPTER 2 PIN FUNCTION 2.1 Pin Function List (1) Port pins Pin Name Function After Reset Alternate Function P00 to P04 Port 0 Input INTP0 to INTP4 7-bit I/O port P05, P06 — Input/output can be specified in 1-bit units. P10 to P15 Input Port 1...
Page 29 CHAPTER 2 PIN FUNCTION (2) Pins other than port pins Pin Name Function After Reset Alternate Function INTP0 to INTP4 Input External maskable interrupt input whose valid edge Input P00 to P04 (rising edge, falling edge, or both rising and falling edges) can be specified SI30 Input...
Page 30: Description Of Pin Functions
CHAPTER 2 PIN FUNCTION 2.2 Description of Pin Functions 2.2.1 P00 to P06 (Port 0) P00 to P06 constitute a 7-bit I/O port. In addition to I/O port pins, P00 to P06 also function as external interrupt inputs. The following operating modes can be specified in 1-bit units. (1) Port mode These pins function as a 7-bit I/O port for which input or output can be specified in 1-bit units using port mode register 0 (PM0).
Page 31: P40 To P47 (Port 4)
CHAPTER 2 PIN FUNCTION 2.2.4 P40 to P47 (Port 4) P40 to P47 constitute an 8-bit I/O port. These pins can be specified as input or output in 1-bit units using port mode register 4 (PM4). On-chip pull-up resistors can be specified by pull-up resistor option register 4 (PU4). An interrupt function via key input is also provided.
Page 32: P120 To P125 (Port 12)
CHAPTER 2 PIN FUNCTION 2.2.8 P120 to P125 (Port 12) P120 to P125 constitute a 6-bit I/O port. In addition to I/O port pins, P120 to P125 also function as serial interface data I/O and clock I/O. The following operating modes can be specified in 1-bit units. (1) Port mode These pins function as an 8-bit I/O port for which input or output can be specified in 1-bit units using port mode register 7 (PM7).
Page 33: Amifc
CHAPTER 2 PIN FUNCTION • VCOH • VHF input • This pin becomes active when the FM mode is selected by software; otherwise the pin is in the status set by bit 3 (VCOHDMD) of the PLL mode select register (PLLMD). If VCOHDMD is reset to 0 (to connect a pull-down resistor), however, the VCOL pin does not become active even if the FM mode is selected.
Page 34: Ic (Mask Rom Version Only)
CHAPTER 2 PIN FUNCTION 2.2.25 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the µ PD178054 Subseries at delivery. Connect it directly to the GND pin with the shortest possible wire in the normal operating mode. When a potential difference is produced between the IC pin and GND pin because the wiring between those two pins is too long or an external noise is input to the IC pin, the user's program may not run normally.
Page 35: Pin I/O Circuits And Recommended Connections Of Unused Pins
CHAPTER 2 PIN FUNCTION 2.3 Pin I/O Circuits and Recommended Connections of Unused Pins Table 2-1 shows the types of the I/O circuits of the respective pins and the recommended connections of the pins when they are not used. For the configuration of the I/O circuit of each pin, refer to Figure 2-1. Table 2-1.
Page 36 CHAPTER 2 PIN FUNCTION Figure 2-1. Pin I/O Circuits (1/2) Type 2 Type 5 Data P-ch IN/OUT Output N-ch disable Input enable Schmitt-triggered input with hysteresis characteristics Type 5-A Type 5-K Pull-up Data P-ch enable P-ch IN/OUT Data P-ch Output N-ch disable IN/OUT...
Page 37 CHAPTER 2 PIN FUNCTION Figure 2-1. Pin I/O Circuits (2/2) Type 25 Type DTS-EO1 P-ch Comparator P-ch – N-ch (Threshold voltage) N-ch Input enable GNDPLL Type 25 Note GNDPLL Note This switch is selectable by software only for the VCOL and VCOH pins. Remark V and GND are the positive power supply and ground pins for all port pins.
Page 38: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The initial value of the memory size switching register (IMS) is CFH. The following values must be set to the registers of each model. Part Number µ PD178053 µ PD178054 µ PD178F054 Value equivalent to mask ROM version User’s Manual U15104EJ2V0UD...
Page 39: Special Function Registers
CHAPTER 3 CPU ARCHITECTURE (1) µ PD178053 Set the value of the memory size switching register (IMS) to C6H. The initial value is CFH. Figure 3-1. Memory Map of µ PD178053 F F F F H Special function registers (SFRs) 256 ×...
Page 40 CHAPTER 3 CPU ARCHITECTURE (2) µ PD178054 Set the value of the memory size switching register (IMS) to C8H. The initial value is CFH. Figure 3-2. Memory Map of µ PD178054 F F F F H Special function registers (SFRs) 256 ×...
Page 41 CHAPTER 3 CPU ARCHITECTURE (3) µ PD178F054 Set the value of the memory size switching register (IMS) to the value corresponding to that of the mask ROM versions. The initial value is CFH. Figure 3-3. Memory Map of µ PD178F054 F F F F H Special function registers (SFRs)
Page 42: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space Programs and table data are stored in internal program memory space, and are usually addressed by the program counter (PC). The µ PD178054 Subseries has internal ROM (or flash memory) as shown in the following table. Table 3-1.
Page 43: Internal Data Memory Space
CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 3.1.2 Internal data memory space The µ...
Page 44: Data Memory Addressing
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. The address of an instruction to be executed next is addressed by the program counter (PC) (for details, refer to 3.3 Instruction Address Addressing).
Page 45 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Data Memory Addressing of µ PD178054 F F F F H Special function registers (SFRs) SFR addressing 256 × 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General-purpose registers Register addressing...
Page 46 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Data Memory Addressing of µ PD178F054 F F F F H Special function registers (SFRs) SFR addressing 256 × 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General-purpose registers Register addressing...
Page 47: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The µ PD178054 Subseries units incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 48 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When IE = 0, all the interrupts are disabled (DI) except the non-maskable interrupt. When IE = 1, the interrupts are enabled (EI). At this time, the acknowledging of interrupts is controlled by the in-service priority flag (ISP), the interrupt mask flag corresponding to each interrupt, and the interrupt priority specification flag.
Page 49 CHAPTER 3 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area (FB00H to FEFFH for µ PD178053, 178054, and 178F054) can be set as the stack area. Figure 3-9.
Page 50: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers The general-purpose registers are mapped at particular address FEE0H to FEFFH in the data memory. They consist of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register and two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE, and HL).
Page 51 CHAPTER 3 CPU ARCHITECTURE Figure 3-12. Configuration of General-Purpose Register (a) Absolute Name 16-bit processing 8-bit processing FEFFH BANK0 FEF8H BANK1 FEE0H BANK2 FEE8H BANK3 FEE0H (b) Function Name 16-bit processing 8-bit processing FEFFH BANK0 FEF8H BANK1 FEF0H BANK2 FEE8H BANK3 FEE0H User’s Manual U15104EJ2V0UD...
Page 52: Special Function Registers (Sfr)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special Function Registers (SFR) Unlike a general-purpose register, each special function register has special functions. SFRs are allocated in the FF00H to FFFFH area. SFRs are can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions.
Page 53 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Registers (1/3) Address Special Function Register (SFR) Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits FF00H Port 0 — FF01H Port 1 — FF03H Port 3 —...
Page 54 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Registers (2/3) Address Special Function Register (SFR) Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits FF6EH Serial I/O shift register 30 SIO30 — — Undefined FF6FH Serial operating mode register 30 CSIM30 —...
Page 55 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Special Function Registers (3/3) Address Special Function Register (SFR) Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits Note 1 FFD0H External access area — Undefined FFDFH FFE0H Interrupt request flag register 0L IF0L FFE1H Interrupt request flag register 0H...
Page 56: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents, and the contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 57: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. The CALL !addr16 and BR !add16 instructions can be used to branch to any location in the memory.
Page 58 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This addressing is used when the CALLT [addr5] instruction is executed.
Page 59: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] User’s Manual U15104EJ2V0UD...
Page 60: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The registers that functions as an accumulator (A and AX) among the general-purpose registers are automatically addressed (implied).
Page 61: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] This addressing mode is used to access a general-purpose register as an operand. The register to be accessed is specified by the register bank select flags (RBS0 and RBS1) and the register specification codes (Rn and RPn) in the operation code.
Page 62: Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory with immediate data in an instruction word is directly addressed. [Operand format] Symbol Description addr16 Label or 16-bit immediate data [Example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 Op code 0 0 0 0 0 0 0 0...
Page 63: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the fixed 256-byte space FE20H to FF1FH. An internal RAM and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 64: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special Function Register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 65: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] This addressing is used to address the memory to be manipulated by using the contents of the register pair specified by the register pair code in an instruction word as the operand address. The register pair specified is in the register bank specified by the register bank select flags (RBS0 and RBS1).
Page 66: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] This addressing mode is used to address a memory location specified by the result of adding the 8-bit immediate data to the contents of the HL register pair which is used as a base register. The HL register pair accessed is the register in the register bank specified by the register bank select flags (RBS0 and RBS1).
Page 67: Based Indexed Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] This addressing mode is used to address a memory location specified by the result of adding the contents of the B or C register specified in the instruction word to the contents of the HL register pair which is used as a base register.
Page 68: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD178054 Subseries units incorporate input, output, and I/O ports consisting of 6, 3, and 53 pins, respectively. Figure 4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations.
Page 69 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Pin Name Function Alternate Function P00 to P04 Port 0 INTP0 to INTP4 7-bit I/O port P05, P06 — Input/output can be specified in 1-bit units. P10 to P15 Input Port 1 ANI0 to ANI5 6-bit input port P30 to P32...
Page 70: Port Configuration
CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration The ports consist of the following hardware. Table 4-2. Port Configuration Item Configuration Control register Port mode register (PMm: m = 0, 3 to 7, 12) Port Total: 62 port pins (6 inputs, 3 outputs, 53 I/Os) 4.2.1 Port 0 Port 0 is a 7-bit I/O port with an output latch.
Page 71: Port 1
CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P05 and P06 Selector PORT Output latch P05, P06 (P05, P06) PM05, PM06 Port mode register Port 0 read signal WR: Port 0 write signal 4.2.2 Port 1 Port 1 is a 6-bit input port. Alternate functions include A/D converter analog input.
Page 72: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 3 Port 3 is an 8-bit I/O port with an output latch. Input or output mode can be specified for port 3 in 1-bit units using port mode register 3 (PM3). Alternate functions include timer input and buzzer output. Reset input sets port 3 to the input mode.
Page 73 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P33 and P34 Alternate function PORT Output latch P33/TI50 (P33, P34) P34/TI51 PM33, PM34 Port mode register Port 3 read signal WR: Port 3 write signal Figure 4-7. Block Diagram of P36 and P37 Selector PORT Output latch...
Page 74: Port 4
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 4 Port 4 is an 8-bit I/O port with an output latch. Input or output mode can be specified for port 4 in 1-bit units using port mode register 4 (PM4). Connection of pull-up resistors can be specified in 1-bit units using pull-up resistor option register 4 (PU4).
Page 75: Port 5
CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of Key Input Detector Key input INTKR detector “1” when MEM = 01H Cautions 1. This register is valid only when the MEM register is set to 01H. 2. Key return can be detected only when all the pins of P40 to P47 are high level. When any one is low level, even if falling edge is generated at the other pins, the key return signal cannot be detected.
Page 76: Port 6
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 6 Port 6 is an 8-bit I/O port with an output latch. Input or output mode can be specified for port 6 in 1-bit units using port mode register 6 (PM6). Reset input sets port 6 to the input mode. Figure 4-11 shows the block diagram of port 6.
Page 77: Port 7
CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 7 Port 7 is an 8-bit I/O port with an output latch. Input or output mode can be specified for port 7 in 1-bit units using port mode register 7 (PM7). Alternate functions include serial interface data I/O, clock I/O, and timer input. Reset input sets port 7 to the input mode.
Page 78 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P71 and P75 Selector PORT Output latch P71/SO30 (P71, P75) P75/SO31 PM71, PM75 Alternate function PM: Port mode register RD: Port 7 read signal WR: Port 7 write signal Figure 4-14. Block Diagram of P72 and P76 Alternate function PORT Output latch...
Page 79 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P73 Selector PORT Output latch (P73) PM73 Port mode register Port 7 read signal WR: Port 7 write signal User’s Manual U15104EJ2V0UD...
Page 80: Port 12
CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 12 Port 12 is a 6-bit I/O port with an output latch. Input or output mode can be specified for port 12 in 1-bit units using port mode register 12 (PM12). Alternate functions include serial interface data I/O and clock I/O. Reset input sets port 12 to the input mode.
Page 81 CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P121 and P124 Selector PORT Output latch P121/SO32 (P121, P124) P124/SO321 PM121, PM124 Alternate function PM: Port mode register RD: Port 12 read signal WR: Port 12 write signal Figure 4-18. Block Diagram of P122 and P125 Alternate function PORT Output latch...
Page 82: Port 13
CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 13 Port 13 is a 3-bit N-ch open-drain output port with an output latch. The pins of this port are also used as timer output pins. Reset input sets port 13 in the general-purpose output port mode. The port 13 block diagram is shown in Figure 4-19.
Page 83: Registers Controlling Port Functions
CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Functions The following two types of registers control the ports. • Port mode registers (PM0, PM3 to PM7, PM12) • Pull-up resistor option register (PU4) (1) Port mode registers (PM0, PM3 to PM7, PM12) These registers are used to set the port input/output mode in 1-bit units.
Page 84 CHAPTER 4 PORT FUNCTIONS Table 4-3. Port Mode Register and Output Latch Settings When Using Alternate Functions Pin Name Alternate Functions PM×× P×× Name × P00 to P04 INTP0 to INTP4 Input × TI50 Input × TI51 Input BEEP0 Output Output ×...
Page 85 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Format of Port Mode Registers Symbol Address After reset PM06 PM05 PM04 PM03 PM02 PM01 PM00 FF20H PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FF24H PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 FF25H PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60...
Page 86 CHAPTER 4 PORT FUNCTIONS (2) Pull-up resistor option register 4 (PU4) This register is used to specify the use of the internal pull-up resistors of port 4. A pull-up resistor can only be used internally for the bit specified by PU4. PU4 can be set with a 1-bit or 8-bit memory manipulation instruction.
Page 87: Port Function Operations
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O ports (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 88: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. This system clock oscillator is connected to 4.5 MHz crystal resonator. At this time, set bit 0 (DTSCK0) of the DTS system clock select register (DTSCK) to 1.
Page 89: Configuration Of Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator consists of the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control register Processor clock control register (PCC) Oscillator System clock oscillator Figure 5-2. Block Diagram of Clock Generator Prescaler System Clock to peripheral hardware...
Page 90: Register Controlling Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.3 Register Controlling Clock Generator The clock generator is controlled by the processor clock control register (PCC). PCC sets the CPU clock. PCC is set with a 1-bit or 8-bit memory manipulation instruction. Reset input sets PCC to 04H. Figure 5-3.
Page 91: System Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 System clock oscillator The system clock oscillator oscillates with a crystal resonator (4.5 MHz TYP.) connected to the X1 and X2 pins. Figure 5-4 shows an external circuit of the system clock oscillator. Figure 5-4.
Page 92 CHAPTER 5 CLOCK GENERATOR Figure 5-5 shows examples of incorrectly connected resonators. Figure 5-5. Examples of Incorrect Resonator Connection (1/2) (a) Wiring of connection (b) Signal lines cross circuits is too long each other PORTn (n = 0, 1, 3 to 7, 12, 13) (c) High fluctuating current is near a (d) Current flows through the ground line signal lines...
Page 93: Divider
CHAPTER 5 CLOCK GENERATOR Figure 5-5. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched 5.4.2 Divider The divider divides the system clock oscillator output (f ) and generates various clocks. User’s Manual U15104EJ2V0UD...
Page 94: Clock Generator Operations
CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operations The clock generator generates the following types of clocks and controls the CPU operating mode, such as the standby mode. • System clock • CPU clock • Clock to peripheral hardware The following clock generator functions and operations are determined by the processor clock control register (PCC).
Page 95: Changing System Clock And Cpu Clock Settings
CHAPTER 5 CLOCK GENERATOR 5.6 Changing System Clock and CPU Clock Settings 5.6.1 Time required for switching between system clock and CPU clock The system clock and CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC).
Page 96: Chapter 6 8-Bit Timer/Event Counters 50 To 53
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.1 Functions of 8-Bit Timer/Event Counters 50 to 53 8-bit timer/event counters 50 to 53 have the following two modes. • Mode in which an 8-bit timer/event counter is used alone (single mode) •...
Page 97 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-1. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus 8-bit compare Selector INTTM50 register 50 (CR50) TI50/P33 Match 8-bit timer counter TO50/P130 50 (TM50) Clear Output latch (P130) Level inversion Selector TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50 TCL502 TCL501 TCL500...
Page 98 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-3. Block Diagram of 8-Bit Timer/Event Counter 52 Internal bus 8-bit compare Selector INTTM52 register 52 (CR52) TI52/P77 Match 8-bit timer counter TO52/P132 52 (TM52) Clear Output latch (P132) Level inversion Selector TCE52 TMC526 TMC524 LVS52 LVR52 TMC521 TOE52 TCL522 TCL521 TCL520...
Page 99: Configuration Of 8-Bit Timer/Event Counters 50 To
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.2 Configuration of 8-Bit Timer/Event Counters 50 to 53 8-bit timer/event counters 50 to 53 consist of the following hardware. Table 6-1. Configuration of 8-Bit Timer/Event Counters 50 to 53 Item Configuration Timer registers 8-bit timer counters 50, 51, 52, and 53 (TM50 to TM53) Registers...
Page 100 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 (2) 8-bit compare registers 50, 51, 52, and 53 (CR50 to CR53) The value set to CR5n is always compared with the value of 8-bit timer counter 5n (TM5n). When the value of a compare register matches the count value of the corresponding counter, an interrupt request (INTTM5n) is generated (in a mode other than PWM mode).
Page 101: Registers Controlling 8-Bit Timer/Event Counters 50 To 53
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.3 Registers Controlling 8-Bit Timer/Event Counters 50 to 53 The following two types of registers control the 8-bit timer/event counters 50 to 53. • Timer clock select registers 50 to 53 (TCL50 to TCL53) •...
Page 102 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 (2) Timer clock select register 53 (TCL53) This register selects the count clock of 8-bit timer counter 53 (TM53). TCL53 is set with an 8-bit memory manipulation instruction. Reset input clears TCL53 to 00H. Figure 6-6.
Page 103 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-7. Format of 8-Bit Timer Mode Control Registers 50 to 52 (TMC50 to TMC52) Symbol <7> <3> <2> <0> Address After reset TMC50 TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50 FF85H <7>...
Page 104 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 (4) 8-bit timer mode control register 53 (TMC53) The TMC53 register is used for the following. <1> Controlling count operation of 8-bit timer counter 53 (TM53) <2> Selecting single mode or cascade mode TMC53 can be set with a 1-bit or 8-bit memory manipulation instruction.
Page 105: Operations Of 8-Bit Timer/Event Counters 50 To 53
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.4 Operations of 8-Bit Timer/Event Counters 50 to 53 6.4.1 Operation as interval timer (8-bit) The 8-bit timer/event counter operates as an interval timer that repeatedly generates an interrupt request at the interval specified by the count value set in advance in 8-bit compare register 5n (CRn).
Page 106: Interval Time
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-9. Timing of Interval Timer Operation (1/3) (a) Basic operation Count clock TM5n count value Count starts Cleared Cleared CR5n TCE5n INTTM5n Interrupt request acknowledged Interrupt request acknowledged TO5n Interval time Interval time Interval time Remarks 1.
Page 107 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-9. Timing of Interval Timer Operation (2/3) (b) When CR5n = 00H Count clock TM5n CR5n TCE5n INTTM5n TO5n Interval time (c) When CR5n = FFH Count clock TM5n CR5n TCE5n INTTM5n Interrupt acknowledged Interrupt...
Page 108 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-9. Timing of Interval Timer Operation (3/3) (d) Operation when CR5n is changed (M < N) Count clock TM5n N 00H CR5n TCE5n INTTM5n TO5n CR5n is changed. TM5n overflows because M < N (e) Operation when CR5n is changed (M >...
Page 109: Operation As External Event Counter (Timers 50 To 52)
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.4.2 Operation as external event counter (timers 50 to 52) The external event counter counts the number of clock pulses input from an external source to the TI5n pin using 8-bit timer counter 5n (TM5n). Each time the valid edge specified by timer clock select register 5n (TCL5n) has been input to TI5n, the value of TM5n is incremented.
Page 110: Square Wave Output Operation (8-Bit Resolution) (Timers 50 To 52)
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.4.3 Square wave output operation (8-bit resolution) (timers 50 to 52) 8-bit timer/event counter TM5n can be used to output a square wave with any frequency at time interval specified by the value set in advance in 8-bit compare register 5n (CR5n). When bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) is set to 1, the output status of TO5n is inverted at the interval specified by the count value set in advance to CR5n.
Page 111: 8-Bit Pwm Output Operation (Timers 50 To 52)
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.4.4 8-bit PWM output operation (timers 50 to 52) The 8-bit timer/event counter can be used for PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set to 1. A pulse with a duty factor determined by the value set in 8-bit compare register 5n (CR5n) is output from TO5n.
Page 112 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-12. Operation Timing of PWM Output (a) Basic operation (when active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H CR5n TCE5n INTTM5n...
Page 113 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 (2) Operation when CR5n is changed Figure 6-13. Timing of Operation When CR5n Is Changed (a) If value of CR5n is changed from N to M before overflow of TM5n Count clock TM5n N N + 1 N + 2 FFH 00H 01H...
Page 114: Interval Timer Operation (16-Bit)
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 6.4.5 Interval timer operation (16-bit) When using the 8-bit timer/counters as a 16-bit timer, be sure to use a combination of timers 50 and 51 or timers 52 and 53. The following section describes the case when using timers 50 and 51. When using timers 52 and 53, read “50”...
Page 115: Notes On 8-Bit Timer/Event Counters 50 To 53
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 Figure 6-14. Operation Timing of 16-Bit Resolution Cascade Mode (Timers 50 and 51) Count clock TM50 N N + 1 FFH 00H FFH 00H FFH 00H 01H N 00H 01H A 00H TM51 M –...
Page 116 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53 (2) Operation after changing compare register during timer count operation If a new value of 8-bit compare register 5n (CR5n) is less than the value of 8-bit timer counter 5n (TM5n), counting continues, and TM5n overflows and starts counting from 0. If the new value of CR5n (M) is less than the old value (N), therefore, it is necessary to restart the timer after changing CR5n.
Page 117: Chapter 7 Basic Timer
CHAPTER 7 BASIC TIMER The basic timer is used for time management during program execution. 7.1 Function of Basic Timer The basic timer generates an interrupt request signal (INTBTM0) at time intervals of 100 ms. 7.2 Configuration of Basic Timer Figure 7-1.
Page 118: Operation Of Basic Timer
CHAPTER 7 BASIC TIMER 7.3 Operation of Basic Timer An example of the operation of the basic timer is shown below. In this example, the basic timer operates as an interval timer that repeatedly generates an interrupt at time intervals of 100 ms.
Page 119: Chapter 8 Watchdog Timer
CHAPTER 8 WATCHDOG TIMER 8.1 Functions of Watchdog Timer The watchdog timer has the following functions. • Watchdog timer • Interval timer • Selecting oscillation stabilization time Caution Select the watchdog timer mode or the interval timer mode using the watchdog timer mode register (WDTM).
Page 120 CHAPTER 8 WATCHDOG TIMER (1) Watchdog timer mode An inadvertent program loop is detected. Upon detection of the inadvertent program loop, a non-maskable interrupt request or reset can be generated. Table 8-1. Watchdog Timer Inadvertent Program Loop Detection Times Inadvertent Program Loop Detection Time (910 µ...
Page 121: Configuration Of Watchdog Timer
CHAPTER 8 WATCHDOG TIMER 8.2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 8-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) Oscillation stabilization time select register (OSTS) 8.3 Registers Controlling Watchdog Timer The following three types of registers are used to control the watchdog timer.
Page 122 CHAPTER 8 WATCHDOG TIMER (1) Watchdog timer clock select register (WDCS) This register sets the watchdog timer and overflow time of the interval timer. WDCS is set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears WDCS to 00H. Figure 8-2.
Page 123 CHAPTER 8 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears WDTM to 00H. Figure 8-3. Format of Watchdog Timer Mode Register (WDTM) After reset <7>...
Page 124 CHAPTER 8 WATCHDOG TIMER (3) Oscillation stabilization time select register (OSTS) This register is used to select the time required for oscillation to stabilize after the RESET signal has been input or the STOP mode has been released. This register is set with an 8-bit memory manipulation instruction. Reset input sets OSTS to 04H.
Page 125: Operations Of Watchdog Timer
CHAPTER 8 WATCHDOG TIMER 8.4 Operations of Watchdog Timer 8.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer operates to detect any inadvertent program loop. The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to 2 (WDCS0 to WDCS2) of timer clock select register 2 (WDCS).
Page 126: Interval Timer Operation
CHAPTER 8 WATCHDOG TIMER 8.4.2 Interval timer operation The watchdog timer operates as an interval timer that generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. The count clock (interval time) can be selected by using bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select register (WDCS).
Page 127: Chapter 9 Buzzer Output Controller
CHAPTER 9 BUZZER OUTPUT CONTROLLER 9.1 Functions of Buzzer Output Controllers The µ PD178054 Subseries has the following two types of buzzer output controllers. • BEEP0 • BUZ BEEP0 outputs a square wave of the buzzer frequency selected by BEEP clock select register 0 (BEEPCL0) from the BEEP0/P36 pin.
Page 128: Configuration Of Buzzer Output Controllers
CHAPTER 9 BUZZER OUTPUT CONTROLLLER 9.2 Configuration of Buzzer Output Controllers The buzzer output controllers consist of the following hardware. Table 9-1. Configuration of Buzzer Output Controllers (1) BEEP0 Item Configuration Control register BEEP clock select register 0 (BEEPCL0) (2) BUZ Item Configuration Control register...
Page 129: Buz
CHAPTER 9 BUZZER OUTPUT CONTROLLER 9.3.2 BUZ BUZ is controlled by the following register. • Clock output select register (CKS) (1) Clock output select register (CKS) This register enables/disables buzzer output and sets the clock of the buzzer output. CKS is set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H.
Page 130: Chapter 10 A/D Converter
CHAPTER 10 A/D CONVERTER 10.1 Functions of A/D Converter The A/D converter converts analog inputs into digital values and consists of 6 channels (ANI0 to ANI5) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in 8-bit A/D conversion result register 3 (ADCR3).
Page 131 CHAPTER 10 A/D CONVERTER Figure 10-1. Block Diagram of A/D Converter ANI0/P10 Sample & hold circuit ANI1/P11 Voltage comparator ANI2/P12 ADCS3 ANI3/P13 ANI4/P14 ANI5/P15 Successive approximation register (SAR) INTAD3 Controller Voltage Controller comparator Power-fail comparison threshold A/D conversion result value register 3 (PFT3) register 3 (ADCR3) ADS33 ADS32 ADS31 ADS30 ADCS3...
Page 132 CHAPTER 10 A/D CONVERTER (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When up to the least significant bit (LSB) is set (termination of A/D conversion), the SAR contents are transferred to the A/D conversion result register.
Page 133: Registers Controlling A/D Converter
CHAPTER 10 A/D CONVERTER 10.3 Registers Controlling A/D Converter The following three registers control the A/D converter. • A/D converter mode register 3 (ADM3) • Analog input channel specification register 3 (ADS3) • Power-fail comparison mode register 3 (PFM3) (1) A/D converter mode register 3 (ADM3) This register selects the conversion time of the analog input to be converted and starts or stops the conversion operation.
Page 134 CHAPTER 10 A/D CONVERTER (2) Analog input channel specification register 3 (ADS3) This register specifies the input channel of the analog voltage to be converted. ADS3 is set with an 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 10-3.
Page 135 CHAPTER 10 A/D CONVERTER (3) Power-fail comparison mode register 3 (PFM3) PFM3 is set with a 1-bit or 8-bit memory manipulation instruction. Reset input clears this register to 00H. Figure 10-4. Format of Power-Fail Comparison Mode Register 3 (PFM3) Symbol <7>...
Page 136: Operations Of A/D Converter
CHAPTER 10 A/D CONVERTER 10.4 Operations of A/D Converter 10.4.1 Basic operations of A/D converter (1) Select one channel for A/D conversion with A/D converter analog input channel specification register 3 (ADS3). (2) Sample the voltage input to the selected analog input channel with the sample & hold circuit. (3) Sampling for the specified period of time sets the sample &...
Page 137 CHAPTER 10 A/D CONVERTER Figure 10-5. A/D Converter Basic Operation Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR3 result INTAD3 A/D conversion operations are performed continuously until bit 7 (ADCS3) of the ADM is reset (0) by software. If a write to ADM3 or ADS3 is performed during an A/D conversion operation, the conversion operation is initialized, and if the ADCS3 bit is set (1), conversion starts again from the beginning.
Page 138: Input Voltage And Conversion Results
CHAPTER 10 A/D CONVERTER 10.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI5) and the A/D conversion result (the value stored in A/D conversion result register 3 (ADCR3) is shown by the following expression. ×...
Page 139: A/D Converter Operating Mode
CHAPTER 10 A/D CONVERTER 10.4.3 A/D converter operating mode The A/D converter has the following two modes: • A/D conversion operation mode: In this mode, the voltage applied to the analog input pin selected from ANI0 to ANI5 is converted into a digital signal. The result of the A/D conversion is stored in A/D conversion result register 3 (ADCR3), and at the same time, an interrupt request signal (INTAD3) is generated.
Page 140 CHAPTER 10 A/D CONVERTER Figure 10-7. A/D Conversion Operation Conversion start ADM3 rewrite ADS3 rewrite ADCS3 = 1 ADCS3 = 0 Stop ANIn ANIn ANIn ANIm ANIm A /D conversion Conversion suspended Conversion results are Stop not stored Note ADCR3 Undefined ANIn ANIm...
Page 141 CHAPTER 10 A/D CONVERTER (2) Power-fail comparison mode In the power-fail comparison mode, the digital value converted from analog input is compared in units of 8 bits. If the result of the comparison matches the condition set by bit 6 (PFCM3) of power-fail comparison mode register 3 (PFM3), an interrupt request (INTAD3) is generated.
Page 142 CHAPTER 10 A/D CONVERTER Figure 10-9. A/D Conversion Operation in Power-Fail Comparison Mode (1/3) (1) In normal mode (other than HALT mode) Conversion starts ADS3 rewrite ADM3 rewrite ADCS3 = 1 ADCS3 = 0 A/D conversion Stop ANIn ANIn ANIn ANIn ANIm ANIm...
Page 143 CHAPTER 10 A/D CONVERTER Figure 10-9. A/D Conversion Operation in Power-Fail Comparison Mode (2/3) (2) In HALT repeat mode (when generation of interrupt (INTAD3) is used to release HALT mode) Conversion starts ADIF clear ADM3 rewrite Note 2 HALT instruction ADCS3 = 1 PFHRM3 = 1 ADCS3 = 0...
Page 144 CHAPTER 10 A/D CONVERTER Figure 10-9. A/D Conversion Operation in Power-Fail Comparison Mode (3/3) (3) In HALT repeat mode (when generation of interrupt (INTAD3) is not used to release HALT mode) Note 2 HALT instruction Conversion starts ADIF clear HALT operation ADCS3 = 1 PFHRM3 = 1 Interrupt request (INTAD) does...
Page 145: Notes On A/D Converter
CHAPTER 10 A/D CONVERTER 10.5 Notes on A/D Converter (1) Current consumption in standby mode The A/D converter is stopped in the standby mode. At this time, the current consumption can be reduced by stopping the conversion operation (by resetting bit 7 (ADCS3) of A/D converter mode register 3 (ADM3) to Figure 10-10 shows how to reduce the current consumption in the standby mode.
Page 146 CHAPTER 10 A/D CONVERTER (4) ANI0 to ANI5 The analog input pins ANI0 to ANI5 also function as input port (P10 to P15) pins. When A/D conversion is performed with any of pins ANI0 to ANI5 selected, be sure not to execute a PORT1 input instruction while conversion is in progress, as this may reduce the conversion resolution.
Page 147: Chapter 11 Serial Interfaces Sio30 To Sio32
CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 11.1 Functions of Serial Interfaces SIO30 to SIO32 The serial interface SIO3n has the following two modes. (1) Operation stop mode This mode is used when serial transfer is not performed. For details, refer to 11.4.1 Operation stop mode. (2) 3-wire serial I/O mode (MSB first) In this mode, 8-bit data is transferred by using three lines: serial clock (SCK3n), serial output (SO3n), and serial input (SI3n) lines.
Page 148 CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 Figure 11-2. Block Diagram of Serial Interface SIO31 Internal bus Serial I/O shift SI31/P74 register 31 (SIO31) PM75 SO31/P75 P75 output latch Interrupt Serial clock request signal SCK31/P76 INTCSI31 counter generator Serial clock controller Selector PM76...
Page 149: Configuration Of Serial Interfaces Sio30 To Sio32
CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 11.2 Configuration of Serial Interfaces SIO30 to SIO32 The serial interface SIO3n consists of the following hardware. Table 11-1. Configuration of Serial Interfaces SIO30 to SIO32 Item Configuration Register Serial I/O shift registers 30 to 32 (SIO30 to SIO32) Control registers Serial operating mode registers 30 to 32 (CSIM30 to CSIM32) Serial port select register 32 (SIO32SEL)
Page 150: Registers Controlling Serial Interfaces Sio30 To Sio32
CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 11.3 Registers Controlling Serial Interfaces SIO30 to SIO32 The following registers control the serial interface SIO3n. • Serial operating mode registers 30 to 32 (CSIM30 to CSIM32) • Serial port select register 32 (SIO32SEL) (1) Serial operating mode register 30 to 32 (CSIM30 to CSIM32) These registers select the serial clock of SIO3n and an operating mode, and enable or disable the operation.
Page 151 CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 Caution Set the port mode register (PM××) as follows in the 3-wire serial I/O mode. Set the output latch to 0. Serial Type Serial Interface Serial Interface Serial Interface SIO32 SIO30 SIO31 Operation Mode S32SEL0 = 0 S32SEL0 = 1 Serial clock output...
Page 152: Operations Of Serial Interfaces Sio30 To Sio32
CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 11.4 Operations of Serial Interfaces SIO30 to SIO32 This section explains the two modes of the serial interfaces SIO30 to SIO32. 11.4.1 Operation stop mode In this mode, serial transfer is not performed. The alternate-function pins used for the serial interface can be used as ordinary I/O port pins.
Page 153: 3-Wire Serial I/O Mode
CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 11.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connecting a peripheral I/O or display controller equipped with a clocked serial interface. In this mode, communication is executed by using three lines: serial clock (SCK3n), serial output (SO3n), and serial input (SI3n) lines.
Page 154 CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 Caution Set the port mode register (PM××) as follows in the 3-wire serial I/O mode. Set the output latch to 0. Serial Type Serial Interface Serial Interface Serial Interface SIO32 SIO30 SIO31 Operation Mode S32SEL0 = 0 S32SEL0 = 1 Serial clock output...
Page 155 CHAPTER 11 SERIAL INTERFACES SIO30 TO SIO32 (3) Starting transfer Serial transfer is started by writing (or reading) the transfer data to serial I/O shift register 3n (SIO3n) when the following conditions are satisfied. • Operation control bit of SIO3n (bit 7 (CSIE3n) of serial operation mode register 3n (CSIM3n)) = 1 •...
Page 156: Chapter 12 Interrupt Functions
CHAPTER 12 INTERRUPT FUNCTIONS 12.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupts This type of interrupt is acknowledged unconditionally even if interrupts are disabled. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a standby release signal.
Page 157 CHAPTER 12 INTERRUPT FUNCTIONS Table 12-1. Interrupt Sources Interrupt Type Default Interrupt Source Internal/ Vector Basic Note 1 Priority External Table Configuration Name Trigger Note 2 Address Type Non-maskable – INTWDT Overflow of watchdog timer Internal 0004H (when watchdog timer mode 1 is selected) Maskable INTWDT Overflow of watchdog timer...
Page 158 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal bus Vector table Interrupt Priority controller address request generator Standby release signal (B) Internal maskable interrupt Internal bus Vector table address Priority controller Interrupt generator request...
Page 159 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-1. Basic Configuration of Interrupt Function (2/2) (D) Software interrupt Internal bus Vector table Interrupt Priority controller address request generator Remark Interrupt request flag Interrupt enable flag ISP: Inservice priority flag MK: Interrupt mask flag PR: Priority specification flag User’s Manual U15104EJ2V0UD...
Page 160: Registers Controlling Interrupt Functions
CHAPTER 12 INTERRUPT FUNCTIONS 12.3 Registers Controlling Interrupt Functions The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H) • Interrupt mask flag register (MK0L, MK0H) • Priority specification flag register (PR0L, PR0H) •...
Page 161 CHAPTER 12 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input.
Page 162 CHAPTER 12 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing and to set standby clear enable/disable. MK0L and MK0H are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting.
Page 163 CHAPTER 12 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H) The priority specification flags are used to set the corresponding maskable interrupt priority orders. PR0L and PR0H are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.
Page 164 CHAPTER 12 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers set the valid edge for INTP0 to INTP4. EGP and EGN are set with a 1-bit or 8-bit memory manipulation instructions. Reset input clears these registers to 00H.
Page 165 CHAPTER 12 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register that holds the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt servicing are mapped.
Page 166: Interrupt Servicing Operations
CHAPTER 12 INTERRUPT FUNCTIONS 12.4 Interrupt Servicing Operations 12.4.1 Non-maskable interrupt request acknowledgement operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledgement disabled state. It does not undergo interrupt priority control and has the highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the acknowledged interrupt is saved to the stack, the program status word (PSW) and the program counter (PC), in that order, the IE and ISP flags are reset to 0, and the vector table contents are loaded into PC and branched.
Page 167 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-7. Flowchart from Generation of Non-Maskable Interrupt Request to Acknowledgement Start WDTM4 = 1 (with watchdog timer mode selected)? Interval timer Overflow in WDT? WDTM3 = 0 (with non-maskable interrupt request selected)? Reset processing Interrupt request generation WDT interrupt servicing? Interrupt request held pending...
Page 168 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-9. Non-Maskable Interrupt Request Acknowledgement Operation If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main routine NMI request NMI request NMI request is held pending. Execution of one instruction Pending NMI request is serviced.
Page 169: Maskable Interrupt Request Acknowledgement Operation
CHAPTER 12 INTERRUPT FUNCTIONS 12.4.2 Maskable interrupt request acknowledgement operation A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag of the interrupt request is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1).
Page 170 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-10. Interrupt Request Acknowledgement Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request pending Yes (High priority) ××PR = 0? No (Low priority) Any high- priority interrupt request among simultaneously simultaneously generated ××...
Page 171 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-11. Interrupt Request Acknowledgement Timing (Minimum Time) 6 clocks PSW and PC save, Interrupt CPU processing Instruction Instruction jump to interrupt servicing servicing program ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: : CPU clock) Figure 12-12.
Page 172: Software Interrupt Request Acknowledgement Operation
CHAPTER 12 INTERRUPT FUNCTIONS 12.4.3 Software interrupt request acknowledgement operation A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, it is saved to the stack, the program status word (PSW) and program counter (PC), in that order, the IE flag is reset to 0 and the contents of the vector tables (003EH and 003FH) are loaded into the PC and branched.
Page 173: Multiple Interrupt Servicing
CHAPTER 12 INTERRUPT FUNCTIONS 12.4.4 Multiple interrupt servicing The acknowledgement of another interrupt request while an interrupt is being serviced is called multiple interrupt servicing. Multiple interrupt servicing does not take place unless the interrupts (except the non-maskable interrupt) are abled to be acknowledged (IE = 1).
Page 174 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-13. Multiple Interrupt Servicing Example (1/2) Example 1. Example where multiple interrupt occurs two times Main processing INTxx INTyy INTzz service service service IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0)
Page 175 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-13. Multiple Interrupt Servicing Example (2/2) Example 3. Example where multiple interrupt does not occur because interrupts are not enabled Main processing INTxx INTyy service service IE = 0 INTyy (PR = 0) INTxx (PR = 0) RETI IE = 0 1 instruction...
Page 176: Pending Interrupt Requests
CHAPTER 12 INTERRUPT FUNCTIONS 12.4.5 Pending interrupt requests Even if an interrupt request is generated, the following instructions hold it pending. • MOV PSW, #byte • MOV A, PSW • MOV PSW, A • MOV1 PSW.bit, CY • MOV1/AND1/OR1/XOR1 CY, PSW.bit •...
Page 177: Chapter 13 Pll Frequency Synthesizer
CHAPTER 13 PLL FREQUENCY SYNTHESIZER 13.1 Function of PLL Frequency Synthesizer The PLL (Phase Locked Loop) frequency synthesizer is used to lock the frequency in the MF (Middle Frequency), HF (High Frequency), and VHF (Very High Frequency) ranges to a specific frequency by means of phase difference comparison.
Page 178 CHAPTER 13 PLL FREQUENCY SYNTHESIZER Table 13-1. Division Mode, Input Pin, and Division Value Division Mode Pin Used Value That Can Be Set Direct division (MF) VCOL 32 to 2 –1 Pulse swallow (HF) VCOL 1024 to 2 –1 Pulse swallow (VHF) VCOH 1024 to 2 –1...
Page 179: Configuration Of Pll Frequency Synthesizer
CHAPTER 13 PLL FREQUENCY SYNTHESIZER 13.2 Configuration of PLL Frequency Synthesizer The PLL frequency synthesizer consists of the following hardware. Table 13-2. Configuration of PLL Frequency Synthesizer Item Configuration Data registers PLL data register L (PLLRL) PLL data register H (PLLRH) PLL data register 0 (PLLR0) Control registers PLL mode select register (PLLMD)
Page 180 CHAPTER 13 PLL FREQUENCY SYNTHESIZER (1) PLL data register L (PLLRL), PLL data register H (PLLRH), and PLL data register 0 (PLLR0) These registers set the division value of the PLL frequency synthesizer. The division value of the PLL frequency synthesizer is made up of 17 bits. The higher 16 bits of this value are set by PLL data register L (PLLRL) and PLL data register H (PLLRH).
Page 181: Registers Controlling Pll Frequency Synthesizer
CHAPTER 13 PLL FREQUENCY SYNTHESIZER 13.3 Registers Controlling PLL Frequency Synthesizer The PLL frequency synthesizer is controlled by the following four registers. • PLL mode select register (PLLMD) • PLL reference mode register (PLLRF) • PLL unlock F/F judge register (PLLUL) •...
Page 182 CHAPTER 13 PLL FREQUENCY SYNTHESIZER (2) PLL reference mode register (PLLRF) This register selects the reference frequency f of the PLL frequency synthesizer and sets the disabled status of the PLL frequency synthesizer. PLLRF is set with 1-bit or 8-bit memory manipulation instruction. The value of this register is set to 0FH after reset and in the STOP mode.
Page 183 CHAPTER 13 PLL FREQUENCY SYNTHESIZER (3) PLL unlock F/F judge register (PLLUL) This register detects whether the PLL frequency synthesizer is in the unlock status. Because this register is an R&RESET register, it is reset to 0 after it has been read. Note 1 Reset input sets this register to 0×H In the STOP and HALT modes, this register holds the value immediately before the STOP or HALT mode was...
Page 184 CHAPTER 13 PLL FREQUENCY SYNTHESIZER (4) PLL data transfer register (PLLNS) This register transfers the values of the PLL data registers (PLLRL, PLLRH, and PLLR0) to the programmable counter and swallow counter. The value of this register is 00H after reset and in the STOP mode. In the HALT mode, this register holds the previous value immediately before the HALT mode is set.
Page 185: Operation Of Pll Frequency Synthesizer
CHAPTER 13 PLL FREQUENCY SYNTHESIZER 13.4 Operation of PLL Frequency Synthesizer 13.4.1 Operation of each block of PLL frequency synthesizer (1) Operation of input select block and programmable divider The input select block and programmable divider select the input pin and division mode of the PLL frequency synthesizer and divide the frequency in the selected division mode, according to the setting of the PLL mode select register (PLLMD).
Page 186 CHAPTER 13 PLL FREQUENCY SYNTHESIZER Figure 13-7. Configuration of Reference Frequency Generator PLLRF3 to PLLRF0 4-16 decoder PLL disable signal Divider 1 kHz 4.5 MHz 3 kHz 9 kHz φ To -DET 25 kHz 50 kHz (3) Operation of phase comparator ( φ -DET) Figure 13-8 shows the configuration of the phase comparator ( φ...
Page 187 CHAPTER 13 PLL FREQUENCY SYNTHESIZER Figure 13-9. Relationship Between f , UP, and DW (a) If f advances f in phase (b) If f advances f in phase (c) If f and f are in phase (d) If f is lower than f (4) Operation of charge pump The charge pump outputs the result of the up request (UP) or down request (DW) signal from the phase comparator ( φ...
Page 188 CHAPTER 13 PLL FREQUENCY SYNTHESIZER Table 13-3. Error Out Output Signal Relationship Between Divided Frequency Error Out Output Signal and Reference Frequency f When f > f Low level When f < f High level When f Floating (high impedance) Figure 13-10.
Page 189: Operation To Set N Value Of Pll Frequency Synthesizer
CHAPTER 13 PLL FREQUENCY SYNTHESIZER (5) Operation of unlock F/F The unlock F/F detects the unlock status of the PLL frequency synthesizer. The unlock status of the PLL frequency synthesizer is detected from the up request signal UP and down request signal DW of the phase comparator ( φ...
Page 190 CHAPTER 13 PLL FREQUENCY SYNTHESIZER Data is set to the PLL data registers (PLLR and PLLR0) as follows. PLLR PLLR0 PLLSCN PLLRH PLLRL b6 b5 b4 b3 b2 b1 b0 Programmable counter value Don’t care Fixed to 0 After setting the above PLL data registers (PLLR and PLLR0), data must be transferred to the programmable counter by setting bit 0 (PLLNS0) of the PLL data transfer register (PLLNS).
Page 191 CHAPTER 13 PLL FREQUENCY SYNTHESIZER Because the least significant bit of the division value N must be set to bit 7 (PLLSCN) of PLL data register 0 (PLLR0), data must be set by shifting the result of the above calculation 1 bit to the right. Data is set to the PLL data registers (PLLR and PLLR0) as follows.
Page 192 CHAPTER 13 PLL FREQUENCY SYNTHESIZER (3) Pulse swallow mode (VHF) (a) Calculating division value N (value set to PLL data register) VCOH where, : Input frequency of VCOH pin VCOH Reference frequency (b) Example of setting PLL data register An example of setting the PLL data register to receive broadcasting stations in the following FM band is shown below.
Page 193 CHAPTER 13 PLL FREQUENCY SYNTHESIZER After setting the above PLL data registers (PLLR and PLLR0), data must be transferred to the programmable counter and swallow counter by setting bit 0 (PLLNS0) of the PLL data transfer register (PLLNS). In this example, a value of half the N value is set to the higher 16 bits of the PLL data register (PLLR) by shifting the N value resulting from calculation 1 bit to the right.
Page 194: Pll Disable Status
CHAPTER 13 PLL FREQUENCY SYNTHESIZER 13.5 PLL Disable Status The PLL frequency synthesizer can be stopped (PLL disabled status) by performing any of the following settings while the PLL frequency synthesizer is operating. • Setting value of bit 3 (PLLRF3) of the PLL reference mode register (PLLRF) to 1 to set PLL disabled status •...
Page 195: Chapter 14 Frequency Counter
CHAPTER 14 FREQUENCY COUNTER 14.1 Function of Frequency Counter The frequency counter counts the intermediate frequency (IF) of a tuner. The intermediate frequency input to the FMIFC or AMIFC pin is counted for a specific time (1 ms, 4 ms, 8 ms, or open) by a 16-bit counter.
Page 196 CHAPTER 14 FREQUENCY COUNTER Figure 14-1. Block Diagram of Frequency Counter Gate time control block FMIFC IF counter Start/stop Input select register control block block (IFCR) block AMIFC IF counter IF counter IF counter mode select gate judge control register register (IFCMD) register (IFCJG) (IFCCR)
Page 197: Registers Controlling Frequency Counter
CHAPTER 14 FREQUENCY COUNTER 14.3 Registers Controlling Frequency Counter The frequency counter is controlled by the following three registers. • IF counter mode select register (IFCMD) • IF counter control register (IFCCR) • IF counter gate judge register (IFCJG) (1) IF counter mode select register (IFCMD) This register selects the input pin of the frequency counter, and selects a mode and gate time (count time).
Page 198 CHAPTER 14 FREQUENCY COUNTER (2) IF counter control register (IFCCR) This register starts counting by the IF counter register and clears the IF counter register. IFCCR is set with a 1-bit or 8-bit memory manipulation instruction. The value of this register is reset to 00H after reset and in the STOP mode. In the HALT mode, this register holds the value immediately before the HALT mode is set.
Page 199: Operation Of Frequency Counter
CHAPTER 14 FREQUENCY COUNTER 14.4 Operation of Frequency Counter <1> Select an input pin, mode, and gate time using the IF counter mode select register (IFCMD). Figure 14-5 shows a block diagram of input pin and mode selection. <2> Set bit 0 (IFCRES) of the IF counter control register (IFCCR) to 1, and clear the data of the IF counter register. <3>...
Page 200 CHAPTER 14 FREQUENCY COUNTER Figure 14-6. Gate Timing of Frequency Counter (a) If gate time is set to 1, 4, or 8 ms Internal 1 kHz OPEN 1 ms CLOSE Counting ends if gate time is 1 ms. OPEN 4 ms CLOSE Counting ends if gate time is 4 ms.
Page 201: Notes On Frequency Counter
CHAPTER 14 FREQUENCY COUNTER 14.5 Notes on Frequency Counter (1) Notes on using frequency counter Because signals are input to the frequency counter from an input pin (FMIFC or AMIFC pin) with an AC amplifier as shown in Figure 14-7, cut the DC component of the input signals by using capacitor C. If the FMIFC or AMIFC pin is selected by the IF counter mode select register, switch SW1 turns ON, and switch SW2 turns OFF.
Page 202 CHAPTER 14 FREQUENCY COUNTER (3) Error of frequency counter The error of the frequency counter includes an error of gate time and a count error. (1) Error of gate time The gate time of the frequency counter is created by dividing 4.5 MHz. Therefore, if 4.5 MHz is shifted “+x”...
Page 203: Chapter 15 Standby Function
CHAPTER 15 STANDBY FUNCTION 15.1 Standby Function and Configuration 15.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. System clock oscillator continues oscillation.
Page 204: Register Controlling Standby Function
CHAPTER 15 STANDBY FUNCTION 15.1.2 Register controlling standby function A wait time after the STOP mode is released upon interrupt request until the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. Reset input sets OSTS to 04H.
Page 205: Operations Of Standby Function
CHAPTER 15 STANDBY FUNCTION 15.2 Operations of Standby Function 15.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. The operating status in the HALT mode is described below. Table 15-1. HALT Mode Operating Status Item Status Clock generator...
Page 206 CHAPTER 15 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following three types of sources. (a) Release upon unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out.
Page 207 CHAPTER 15 STANDBY FUNCTION (c) Release by RESET input If the RESET signal is input, the HALT mode is released. As is the case with normal reset operation, the program is executed after branch to the reset vector address. Figure 15-3. HALT Mode Release by RESET Input Wait HALT : 29.1 ms)
Page 208: Stop Mode
CHAPTER 15 STANDBY FUNCTION 15.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. Cautions 1. When the STOP mode is set, the X1 pin is pulled down to GND, and the X2 pin is internally pulled up to V to minimize the leakage current at the crystal oscillator block.
Page 209 CHAPTER 15 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released by the following two types of sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. If interrupt request acknowledgement is enabled after the lapse of oscillation stabilization time, vectored interrupt servicing is carried out.
Page 210 CHAPTER 15 STANDBY FUNCTION (b) Release by RESET input If the RESET signal is input, the STOP mode is released, and after the lapse of oscillation stabilization time, a reset operation is carried out. Figure 15-5. Release by STOP Mode RESET Input Wait STOP : 29.1 ms)
Page 211: Chapter 16 Reset Function
CHAPTER 16 RESET FUNCTION 16.1 Reset Function The following three operations are available to generate the reset signal. (1) External reset input via a RESET pin (2) Internal reset by inadvertent program loop time detection watchdog timer (3) Internal reset by power-on clear (POC) (1) External reset input by RESET pin When a low level is input to the RESET pin, the device is reset, and each hardware unit enters the status shown in Table 16-1.
Page 212 CHAPTER 16 RESET FUNCTION Cautions 1. For an external reset, input a low level for 10 µ s or more to the RESET pin. 2. During reset input, system clock oscillation remains stopped. 3. When the STOP mode is released by RESET input, the STOP mode register contents are held during reset input.
Page 213 CHAPTER 16 RESET FUNCTION Figure 16-2. Timing of Reset by RESET Input (a) In normal operation mode Oscillation Reset period Normal operation Normal operation stabilization (oscillation (reset processing) time wait stop) RESET Internal reset signal Delay Delay High impedance I/O port pin Output port pin (P130 to P132) (b) In STOP mode...
Page 214 CHAPTER 16 RESET FUNCTION Figure 16-3. Timing of Reset due to Watchdog Timer Overflow Normal operation Reset period Oscillation Normal operation (oscillation stabilization (reset processing) Watchdog stop) time wait timer overflow Internal reset signal High impedance I/O port pin Output port pin (P130 to P132) User’s Manual U15104EJ2V0UD...
Page 215 CHAPTER 16 RESET FUNCTION Figure 16-4. Timing of Reset by Power-on Clear (a) At power application Oscillation Reset period Normal operation stabilization (oscillation stop) (reset processing) time wait 4.5 V 3.5 V 2.2 V Power-on clear voltage (3.5 V) Internal reset signal High impedance I/O port pin...
Page 216 CHAPTER 16 RESET FUNCTION Table 16-1. Hardware Status After Reset (1/2) Hardware Status After Reset Note 1 Program counter (PC) Contents of reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Undefined Note 2 Data memory Undefined Note 2...
Page 217 CHAPTER 16 RESET FUNCTION Table 16-1. Hardware Status After Reset (2/2) Hardware Status After Reset A/D converter Mode register 3 (ADM3) A/D conversion result register 3 (ADCR3) Undefined Analog input channel specification register 3 (ADS3) Power-fail comparison mode register 3 (PFM3) Power-fail comparison threshold value register 3 (PFT3) Interrupt Request flag registers (IF0L and IF0H)
Page 218: Power Failure Detection Function
CHAPTER 16 RESET FUNCTION 16.2 Power Failure Detection Function If reset is effected by means of power-on clear, bit 0 (POCM) of the POC status register (POCS) is set to 1. If reset is effected by the RESET pin or the watchdog timer, however, POCM holds the previous status. A power failure status can be detected by detecting this POCM after reset by power-on clear has been cleared (after program execution has been started from address 0000H).
Page 219: Voltage Detection Function
CHAPTER 16 RESET FUNCTION 16.3 4.5 V Voltage Detection Function pin below 4.5 V (4.5 V ±0.3 V). If the voltage on the V This function is used to detect a voltage drop on the V pin drops below 4.5 V (4.5 V ±0.3 V), bit 1 (VM45) of the POC status register (POCS) is set. Note, however, that this 4.5 V voltage detection function does not cause internal reset.
Page 220: Chapter 17 Μ Pd178F054
CHAPTER 17 µ PD178F054 The µ PD178F054 is provided with a flash memory to/from which data can be rewritten/erased with the device mounted on the printed circuit board. The differences between the flash memory ( µ PD178F054) and mask ROM versions ( µ...
Page 221: Memory Size Switching Register (Ims)
CHAPTER 17 µ PD178F054 17.1 Memory Size Switching Register (IMS) The internal memory capacity of the µ PD178F054 can be changed using the memory size switching register (IMS). By using this register, the memory of the µ PD178F054 can be mapped in the same manner as a mask ROM version with a different internal memory capacity.
Page 222: Internal Expansion Ram Size Switching Register (Ixs)
CHAPTER 17 µ PD178F054 17.2 Internal Expansion RAM Size Switching Register (IXS) The internal expansion RAM capacity of the µ PD178F054 can be changed using the internal expansion RAM size switching register (IXS). By using this register, the memory of the µ PD178F054 can be mapped in the same manner as a mask ROM version with a different internal expansion RAM capacity.
Page 223: Flash Memory Programming
CHAPTER 17 µ PD178F054 17.3 Flash Memory Programming The program memory provided in the µ PD178F054 is flash memory. The flash memory can be written on-board, i.e., with the µ PD178F054 mounted on the target system. To do so, connect a dedicated flash programmer (Flashpro III (Part number: FL-PR3, PG-FP3)) to the host machine and target system.
Page 224: Flash Memory Programming Function
CHAPTER 17 µ PD178F054 17.3.2 Flash memory programming function An operation such as writing the flash memory is performed when a command or data is transmitted/received in the selected communication mode. The major flash memory programming functions are listed in Table 17-5. Table 17-5.
Page 225: Setting Example For Flashpro Iii (Pg-Fp3)
CHAPTER 17 µ PD178F054 17.3.4 Setting example for Flashpro III (PG-FP3) When writing data to flash memory using Flashpro III (PG-FP3), use the following settings. <1> Load parameter file. <2> Select the serial mode and serial cock using the type command. <3>...
Page 226: Chapter 18 Instruction Set
CHAPTER 18 INSTRUCTION SET This chapter describes each instruction set of the µ PD178054 Subseries as list table. For details of its operation and operation code, refer to the 78K/0 Series User’s Manual Instruction (U12326E). User’s Manual U15104EJ2V0UD...
Page 227: Conventions
CHAPTER 18 INSTRUCTION SET 18.1 Conventions 18.1.1 Operand symbols and description Operands are written in the “Operand” column of each instruction in accordance with the description of the instruction operand symbols (refer to the assembler specifications for detail). When there are two or more descriptions, select one of them.
Page 228: Description Of "Operation" Column
CHAPTER 18 INSTRUCTION SET 18.1.2 Description of “operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 229: Operation List
CHAPTER 18 INSTRUCTION SET 18.2 Operation List Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY r ← byte 8-bit data r, #byte – transfer (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte –...
Page 230 CHAPTER 18 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY rp ← word 16-bit data MOVW rp, #word – transfer (saddrp) ← word saddrp, #word sfrp ← word sfrp, #word – AX ←...
Page 231 CHAPTER 18 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY A, CY ← A – byte × × × 8-bit A, #byte – operation (saddr), CY ← (saddr) – byte × ×...
Page 232 CHAPTER 18 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY A ← A byte × 8-bit A, #byte – operation (saddr) ← (saddr) byte × saddr, #byte Note 3 A ← A r ×...
Page 233 CHAPTER 18 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY AX, CY ← AX + word × × × 16-bit ADDW AX, #word – operation AX, CY ← AX – word ×...
Page 234 CHAPTER 18 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY CY ← CY (saddr.bit) × AND1 CY, saddr.bit manipulate CY ← CY sfr.bit × CY, sfr.bit – CY ← CY A.bit ×...
Page 235 CHAPTER 18 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY (SP – 1) ← (PC + 3) , (SP – 2) ← (PC + 3) Call/return CALL !addr16 – PC ← addr16, SP ← SP – 2 (SP –...
Page 236 CHAPTER 18 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY PC ← PC + 3 + jdisp8 if(saddr.bit) = 1 Conditional BT saddr.bit, $addr16 branch PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 –...
Page 237: Instructions Listed By Addressing Type
CHAPTER 18 INSTRUCTION SET 18.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Note 2nd Operand #byte saddr !addr16 [DE]...
Page 238 CHAPTER 18 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note 2nd Operand #word sfrp saddrp !addr16 None 1st Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW...
Page 239 CHAPTER 18 INSTRUCTION SET (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ 2nd Operand !addr16 !addr11 [addr5] $addr16 1st Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP User’s Manual U15104EJ2V0UD...
Page 240: Chapter 19 Electrical Specifications
CHAPTER 19 ELECTRICAL SPECIFICATIONS ° Absolute Maximum Ratings (T = 25 Parameter Symbol Conditions Ratings Unit Supply voltage –0.3 to +6.0 Note 1 PORT –0.3 to V + 0.3 Note 1 –0.3 to V + 0.3 µ PD178F054 only –0.3 to +10.5 Input voltage –0.3 to V + 0.3...
Page 241 CHAPTER 19 ELECTRICAL SPECIFICATIONS ° DC Characteristics (T = –40 to +85 C, V = 3.5 to 5.5 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high P10 to P15, P30 to P32, P35 to P37, P40 to P47, 0.7 V P50 to P57, P60 to P67, P71, P73, P75, P121, P124 P00 to P06, P33, P34, P70, P72, P74, P76, P77,...
Page 242 CHAPTER 19 ELECTRICAL SPECIFICATIONS ° DC Characteristics (T = –40 to +85 C, V = 3.5 to 5.5 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit µ A Input leakage P00 to P06, P10 to P15, = 0 V –3 LIL1 current, low...
Page 243 CHAPTER 19 ELECTRICAL SPECIFICATIONS ° Reference Characteristics (T = –40 to +85 C, V = 4.5 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current When CPU and PLL are operating. Sine wave input to VCOH pin At f = 160 MHz = 0.15 V...
Page 244 CHAPTER 19 ELECTRICAL SPECIFICATIONS ° (2) Serial interface SIO3 (T = –40 to +85 C, V = 3.5 to 5.5 V) (a) 3-wire serial I/O mode (SCK3 ... internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK3 cycle time KCY1 SCK3 high/low-level width /2 –...
Page 245 CHAPTER 19 ELECTRICAL SPECIFICATIONS AC Timing Test Point (Excluding X1 Input) 0.8 V 0.8 V Test points 0.2 V 0.2 V TI Timing TIL5 TIH5 TI50, TI51, TI52 Interrupt Input Timing INTL INTH INTP0 to INTP4 RESET Input Timing RESET User’s Manual U15104EJ2V0UD...
Page 246 CHAPTER 19 ELECTRICAL SPECIFICATIONS Serial Transfer Timing 3-wire serial I/O mode: KCYm SCK3 SIKm KSIm Input data KSOm Output data Remark m = 1, 2 n = 2 User’s Manual U15104EJ2V0UD...
Page 247 CHAPTER 19 ELECTRICAL SPECIFICATIONS ° A/D Converter Characteristics (T = –40 to +85 C, V = 3.5 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution ±1.0 Total conversion = 4.5 to 5.5 V %FSR Notes 1, 2 error ±1.4 %FSR...
Page 248 CHAPTER 19 ELECTRICAL SPECIFICATIONS ° C) ( µ PD178F054 only) Flash Memory Programming Characteristics (V = 3.5 to 5.5 V, T = 10 to 40 (1) Write/delete characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit Note Write current (V pin) When V = 4.5 MHz Note...
Page 249 CHAPTER 19 ELECTRICAL SPECIFICATIONS Flash Write Mode Setting Timing DRPSR RFCF PSRON PSRRF COUNT RESET (input) User’s Manual U15104EJ2V0UD...
Page 250: Chapter 20 Package Drawing
CHAPTER 20 PACKAGE DRAWING 80-PIN PLASTIC QFP (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.13 mm of 17.20±0.20 its true position (T.P.) at maximum material condition. 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20...
Page 251: Chapter 21 Recommended Soldering Conditions
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 21-1. Surface Mounting Type Soldering Conditions µ...
Page 252: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µ PD178054 Subseries. Figure A-1 shows the configuration example of the tools. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT compatibles can be used for PC98-NX series computers.
Page 253 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Configuration of Development Tools (1/2) (1) When using the in-circuit emulator IE-78K0-NS Software Package • Software package Debugging Software Language Processing Software • Assembler package • Integrated debugger • C compiler package • System simulator •...
Page 254 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Configuration of Development Tools (2/2) (2) When using the in-circuit emulator IE-78001-R-A Language Processing Software • Assembler package • C compiler package • C library source file • Device file Debugging Tool • System simulator •...
Page 255: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 This package contains various software tools for 78K/0 Series development. Software package The following tools are included. RA78K0, CC78K0, ID78K0-NS, SM78K0, and various device files Part Number: µ S××××SP78K0 Remark ×××× in the part number differs depending on the OS used. µ...
Page 256: Control Software
APPENDIX A DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and OS used. µ S××××RA78K0 µ S××××CC78K0 ×××× Host Machine Supply Medium AB13 PC-9800 series, Windows (Japanese version) 3.5-inch 2HD FD BB13 IBM PC/AT compatibles Windows (English version) AB17 Windows (Japanese version)
Page 257: Debugging Tools (Hardware)
APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) (1/2) (1) When using the in-circuit emulator IE-78K0-NS IE-78K0-NS The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using a 78K/0 Series product. It corresponds to integrated debugger (ID78K0-NS).
Page 258 APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) (2/2) (2) When using the in-circuit emulator IE-78001-R-A The in-circuit emulator serves to debug hardware and software when developing IE-78001-R-A application systems using a 78K/0 Series product. It corresponds to integrated debugger In-circuit emulator (ID78K0).
Page 259: Debugging Tools (Software)
APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) SM78K0 This is a system simulator for the 78K/0S Series. The SM78K0 is Windows-based System simulator software. It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine.
Page 260: Embedded Software
APPENDIX A DEVELOPMENT TOOLS A.7 Embedded Software RX78K0 is a real-time OS conforming to the µ ITRON specifications. RX78K0 Real-time OS Tool (configurator) for generating nucleus of RX78K0 and plural information tables is supplied. Used in combination with an optional assembler package (RA78K0) and device file (DF178054).
Page 261: System Upgrade From Former In-Circuit Emulator For 78K/0 Series To Ie-78001-R-A
Table A-1. System Upgrade Method from Former In-circuit Emulator for 78K/0 Series to IE-78001-R-A Note In-circuit Emulator Owned In-circuit Emulator Cabinet System Upgrade Board to Be Purchased IE-78000-R Required IE-78001-R-BK IE-78000-R-A Not required Note For upgrading a cabinet, send user’s in-circuit emulator to NEC. User’s Manual U15104EJ2V0UD...
Page 262 APPENDIX A DEVELOPMENT TOOLS Drawing for Conversion Socket (EV-9200GC-80) Package and Recommended Board Mounting Pattern Figure A-2. EV-9200GC-80 Package Drawing (for Reference Only) EV-9200GC-80 No.1 pin index EV-9200GC-80-G1E ITEM MILLIMETERS INCHES 18.0 0.709 14.4 0.567 14.4 0.567 18.0 0.709 4-C 2.0 4-C 0.079 0.031 0.236...
Page 263 APPENDIX A DEVELOPMENT TOOLS Figure A-3. EV-9200GC-80 Recommended Board Mounting Pattern (for Reference Only) EV-9200GC-80-P1E ITEM MILLIMETERS INCHES 19.7 0.776 15.0 0.591 0.65 ± 0.02 × 19=12.35 ± 0.05 × 0.748=0.486 +0.001 +0.003 0.026 –0.002 –0.002 0.65 ± 0.02 × 19=12.35 ± 0.05 +0.001 ×...
Page 264: Appendix B Register Index
APPENDIX B REGISTER INDEX B.1 Register Index 8-bit compare register 50 (CR50) ... 100 8-bit compare register 51 (CR51) ... 100 8-bit compare register 52 (CR52) ... 100 8-bit compare register 53 (CR53) ... 100 8-bit timer counter 50 (TM50) ... 99 8-bit timer counter 51 (TM51) ...
Page 265 APPENDIX B REGISTER INDEX Memory size switching register (IMS) ... 221 Oscillation stabilization time select register (OSTS) ... 124, 204 PLL data register (PLLR) ... 190, 191, 192 PLL data register 0 (PLLR0) ... 180 PLL data register H (PLLRH) ... 180 PLL data register L (PLLRL) ...
Page 266 APPENDIX B REGISTER INDEX Timer clock select register 50 (TCL50) ... 101 Timer clock select register 51 (TCL51) ... 101 Timer clock select register 52 (TCL52) ... 101 Timer clock select register 53 (TCL53) ... 102 Watchdog timer clock select register (WDCS) ... 122 Watchdog timer mode register (WDTM) ...
Page 267: Register Index (Symbol)
APPENDIX B REGISTER INDEX B.2 Register Index (Symbol) ADCR3: A/D conversion result register 3 ... 132, 146 ADM3: A/D converter mode register 3 ... 133 ADS3: Analog input channel specification register 3 ... 134 BEEPCL0: BEEP clock select register 0 ... 128 CKS: Clock output select register ...
Page 268 APPENDIX B REGISTER INDEX Port 4 ... 74 Port 5 ... 75 Port 6 ... 76 Port 7 ... 77 P12: Port 12 ... 80 P13: Port 13 ... 82 PCC: Processor clock control register ... 90 PFM3: Power-fail comparison mode register 3 ... 135 PFT3: Power-fail comparison threshold value register 3 ...
Page 269 APPENDIX B REGISTER INDEX WDCS: Watchdog timer clock select register ... 122 WDTM: Watchdog timer mode register ... 123 User’s Manual U15104EJ2V0UD...
Page 270: Appendix C Revision History
APPENDIX C REVISION HISTORY A history of the revisions up to this edition is shown below. “Applied to:” indicates the chapters to which the revision was applied. Edition Description Applied to: Change of µ PD178053, 178054, and 178F054 status from under development to Throughout development completed Modification of Related Documents...
Page 271 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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Mpd178053Mpd178054Mpd178f054

NEC mPD178054 Series User Manual

Chapter 1 Outline

Chapter 2 Pin Function

Chapter 3 Cpu Architecture

Chapter 4 Port Functions

Chapter 5 Clock Generator

Chapter 6 8-Bit Timer/Event Counters 50 to 53

Chapter 7 Basic Timer

Chapter 8 Watchdog Timer

Chapter 9 Buzzer Output Controller

Chapter 10 A/D Converter

Chapter 11 Serial Interfaces Sio30 to Sio32

Chapter 12 Interrupt Functions

Chapter 13 Pll Frequency Synthesizer

Chapter 14 Frequency Counter

Chapter 15 Standby Function

Chapter 16 Reset Function

CHAPTER 17 Μ PD178F054

Chapter 18 Instruction Set

Chapter 19 Electrical Specifications

Chapter 20 Package Drawing

Chapter 21 Recommended Soldering Conditions

Appendix A Development Tools

Appendix B Register Index

Appendix C Revision History

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Summary of Contents for NEC mPD178054 Series