Watchdog Timer Operation In Stop Mode (When "Ring-Osc Can Be Stopped By Software" Is Selected By Mask Option) - NEC 78K0/KD1 Series User Manual

10.4.3 Watchdog timer operation in STOP mode (when "Ring-OSC can be stopped by software" is selected
by mask option)
The watchdog timer stops counting during STOP instruction execution regardless of whether the X1 input clock or
Ring-OSC clock is being used.
(1) When the CPU clock and the watchdog timer operation clock are the X1 input clock (f
instruction is executed
When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released,
counting stops for the oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
and then counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0.
Figure 10-4. Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock)
Normal
operation
CPU operation
f
XP
f
R
Watchdog timer
Operating
(2) When the CPU clock is the X1 input clock (f
clock (f ) when the STOP instruction is executed
R
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0.
(CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock)
Normal
operation
CPU operation
f
XP
f
R
Watchdog timer
Operating Operation stopped
216
CHAPTER 10 WATCHDOG TIMER
STOP Oscillation stabilization time
Oscillation Oscillation stabilization time
stopped (set by OSTS register)
Operation stopped
) and the watchdog timer operation clock is the Ring-OSC
XP
Figure 10-5. Operation in STOP Mode
Oscillation stabilization time
STOP
Oscillation Oscillation stabilization time
stopped (set by OSTS register)
Operating
Preliminary User's Manual U16315EJ1V0UD
) when the STOP
XP
Normal operation
Operating
Normal operation