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(ii) Asynchronous serial interface status registers 0, 1 (ASIS0, ASIS1)
ASISn can be read using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to 00H.
After reset: 00H
7
ASISn
0
(n = 0, 1)
PEn
0
1
FEn
0
1
OVEn
0
1
Notes 1. Even if a stop bit length of two bits has been set to bit 2 (SLn) in the asynchronous serial interface
mode register (ASIMn), stop bit detection during a receive operation only applies to a stop bit length
of 1 bit.
2. Be sure to read the contents of the receive buffer register (RXBn) when an overrun error has
occurred.
Until the contents of RXBn are read, further overrun errors will occur when receiving data.
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CHAPTER 10
SERIAL INTERFACE FUNCTION
R
Address: FFFFF302H, FFFFF312H
6
5
0
0
No parity error
Parity error
(Transmit data parity does not match)
No framing error
Note 1
Framing error
(Stop bit not detected)
No overrun error
Note 2
Overrun error
(Next receive operation was completed before data was read from receive buffer register)
4
3
2
0
0
PEn
Parity Error Flag
Framing Error Flag
Overrun Error Flag
1
0
FEn
OVEn
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