NEC V850/SA1 mPD703015 Preliminary User's Manual page 381

Instruction Set (alphabetical order) (4/4)
Mnemonic Operand
SST.B reg2, rrrrr0111ddddddd
disp7 [ep]
SST.H reg2, rrrrr1001ddddddd
disp8 [ep]
SST.W reg2, rrrrr1010ddddddd
disp8 [ep]
ST.B reg2, rrrrr111010RRRRR
disp16 [reg1] dddddddddddddddd
ST.H reg2, rrrrr111011RRRRR
disp16 [reg1] ddddddddddddddd0
ST.W reg2, rrrrr111011RRRRR
disp16 [reg1] ddddddddddddddd1
STSR regID, reg2 rrrrr111111RRRRR
0000000001000000
SUB reg1, reg2 rrrrr001101RRRRR
SUBR reg1, reg2 rrrrr001100RRRRR
TRAP vector 00000111111iiiii
0000000100000000
TST reg1, reg2 rrrrr001011RRRRR
TST1 bit#3, 11bbb111110RRRRR
disp16 [reg1] dddddddddddddddd
XOR reg1, reg2 rrrrr001001RRRRR
XORI imm16, rrrrr110101RRRRR
reg1, reg2 iiiiiiiiiiiiiiii
Notes 1. ddddddd is the higher 7 bits of dip8.
2. dddddd is the higher 6 bits of disp8.
3. ddddddddddddddd is the higher 15 bits of disp 16.
APPENDIX B LIST OF INSTRUCTION SET
Op Code
adr ← ep + zero-extend (disp7)
Store-memory (adr, GR [reg2], Byte)
adr ← ep + zero-extend (disp8)
Note 1
Store-memory (adr, GR [reg2], Halfword)
adr ← ep + zero-extend (disp8)
Note 2
Store-memory (adr, GR [reg2], Word)
adr ← GR [reg1] + sign-extend (disp16)
Store-memory (adr, GR [reg2], Byte)
adr ← GR [reg1] + sign-extend (disp16)
Store-memory (adr, GR [reg2], Halfword)
Note 3
adr ← GR [reg1] + sign-extend (disp16)
Store-memory (adr, GR [reg2], Word)
Note 3
GR [reg2] ← SR [regID]
GR [reg2] ← GR [reg2] − GR [reg1]
GR [reg2] ← GR [reg2] − GR [reg1]
← (Restored PC)
EIPC
← PSW
EIPSW
← Interrupt code
ECR.EICC
← 1
PSW.EP
← 1
PSW.ID
PC ← 00000040H(vector = 00H to 0FH)
00000050H(vector = 10H to 1FH)
result ← GR [reg2] AND [reg1]
adr ← GR [reg1] + sign-extend (disp16)
Z flag ← Not (Load-memory-bit (adr,
bit#3))
GR [reg2] ← GR [reg2] XOR GR [reg1]
GR [reg2] ← GR [reg1] XOR zero-extend
(imm16)
Execution
Operation
i
1
1
1
1
1
1
1
1
1
4
1
3
1
1
Flag
Clock
r l CY OV S Z
1 1
1 1
1 1
1 1
1 1
1 1
1 1
× × × ×
1 1
× × × ×
1 1
4 4
× ×
1 1 0
×
3 3
× ×
1 1 0
× ×
1 1 0
SAT
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