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5.4.3 EP flag
The EP flag in PSW is a status flag used to indicate that trap processing is in progress. It is set when a trap oc-
curs, and the interrupt is disabled.
After reset: 00000020H
Symbol
31
PSW
EP
0
Trap processing is not in progress
1
Trap processing is in progress
5.5 Exception Trap
The exception trap is an interrupt that is requested when illegal execution of an instruction takes place. In the
V850/SA1, an illegal op code exception (ILGOP: ILeGal OPcode trap) is considered as an exception trap.
• Illegal op code exception: occurs if the subop code field of an instruction to be executed next is not a valid op
5.5.1 Illegal op code definition
An illegal op code is defined to be a 32-bit word with bits 5 to 10 being 111111B and bits 23 to 26 being 0011B to
1111B.
15
13
x
x
x
x : don't care
5.5.2 Operation
If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler rou-
tine:
(1) Saves the restored PC to EIPC.
(2) Saves the current PSW to EIPSW.
(3) Writes an exception code (0060H) to the lower 16 bits (EICC) of ECR.
(4) Sets the EP and ID bits of PSW.
(5) Loads the handler address (00000060H) for the exception trap routine to the PC, and transfers control.
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CHAPTER 5
INTERRUPT/EXCEPTION PROCESSING FUNCTION
0
NMI Processing
code.
12
11
10
5
4
x
x
1
1
1
1
1
1
x
x
8
7
6
5
4
NP EP ID SAT CY OV
0
31
27 26
0
0
1
to
x
x
x
x
x
x
x
x
1
1
1
3
2
1
0
S
Z
23 22
21
20
17
16
1
x
x
x x x x x
1
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