NEC V850/SA1 mPD703015 Preliminary User's Manual page 218

Slave address
register (SVA0)
SDA
Noise elimination
circuit
IIC shift register
N-ch open
drain output
ACK detection circuit
SCL
Noise elimination
Serial clock counter
circuit
Serial clock control circuit
TM2 output
218
CHAPTER 10 SERIAL INTERFACE FUNCTION
Figure 10-7. Block Diagram of I
Internal bus
IIC control register
(IICC0)
IICE LREL WREL
Coincidence
CLEAR
signal
SET
SO latch
D Q
(IIC0)
CL1,
CL0
Data hold
time correction
circuit
Start condition
detection circuit
Stop condition
detection circuit
Serial clock wait
control circuit
f
xx
Prescaler
CLD DAD SMC DFC CL1
Internal bus
2
C
IIC status register
(IICS0)
MSTS ALD
SPIE WTIM ACKE STT SPT
ACK detection
circuit
Wake up control
circuit
Interrupt request
signal generator
IIC clock select
CL0
register (IICCL0)
EXC COI TRC ACKD STD
INTIIC0
SPD