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Figure 10-21 shows the communication reservation timing.
Program processing
Hardware processing
SCL
1
2
3
SDA
IIC0 : IIC shift register
STT : Bit 1 of IIC control register (IICC0)
STD : Bit 1 of IIC status register (IICS0)
SPD : Bit 0 of IIC status register (IICS0)
Communication reservations are accepted via the following timing. After bit 1 (STD) of the IIC status register
(IICS0) is set to "1", a communication reservation can be made by setting bit 1 (STT) of the IIC control register
(IICC0) to "1" before a stop condition is detected.
CHAPTER 10 SERIAL INTERFACE FUNCTION
Figure 10-21. Communication Reservation Timing
STT
=1
Communication
reservation
4
5
6
7
8
Write to
IIC0
Set SPD
Set
and INTIIC0
STD
9
1
Output by master with bus access
2
3
4
5
6
267
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