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Figure 11-2. Format of A/D Converter Mode Register (ADM) (2/2)
ADPS
FR2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
EGA1
0
0
1
1
ADPS
0
1
306
CHAPTER 11
FR1
FR0
0
0
0
288/fxx
0
0
1
216/fxx
0
1
0
168/fxx
0
1
1
120/fxx
1
0
0
96/fxx
1
0
1
72/fxx
1
1
0
60/fxx
1
1
1
48/fxx
0
0
0
288/fxx + 144/fxx
0
0
1
216/fxx + 108/fxx
0
1
0
168/fxx + 84/fxx
0
1
1
120/fxx + 60/fxx
1
0
0
96/fxx + 58/fxx
1
0
1
72/fxx + 36/fxx
1
1
0
60/fxx + 30/fxx
1
1
1
48/fxx + 24/fxx
EGA0
Specification of Edge Detection of External Trigger Signal
0
No edge detection
1
Detects falling edge.
0
Detects rising edge.
1
Detects both rising and falling edges.
A/D Conversion Power Dissipation/Conversion Time Mode Selection
High speed conversion mode
Low speed conversion/low power dissipation mode
A/D CONVERTER
Conversion Time Selection
Clock number
at fxx = 17 MHz
16.9 µ s
12.7 µ s
9.9 µ s
7.1 µ s
5.6 µ s
Setting prohibited
Setting prohibited
Setting prohibited
25.4 µ s
19.1 µ s
14.9 µ s
10.7 µ s
8.4 µ s
Setting prohibited
Setting prohibited
Setting prohibited
at fxx = 8 MHz
36.0 µ s
27.0 µ s
21.0 µ s
15.0 µ s
12.0 µ s
9.0 µ s
7.5 µ s
6.0 µ s
54.0 µ s
40.5 µ s
31.5 µ s
22.5 µ s
18.0 µ s
13.5 µ s
11.3 µ s
9.0 µ s
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