Watchdog Timer Mode Register 2 (Wdtm2) - NEC V850E/RS1 User Manual

17.3.8 Watchdog timer mode register 2 (WDTM2)

This register is a special register and can be written only in a specific sequence. To generate a maska-
ble interrupt (INTWDT2), clear the WDM20 bit of this register to 0.
This register can be read or written in 8-bit or 1-bit units (for details, refer to Chapter 10 "Functions
of Watchdog Timer 2" on page 359).
Cautions: 1. For details of bits WDCS20 to WDCS24, refer to Table 17-3, "Watchdog Timer 2
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Chapter 17 Interrupt/Exception Processing Function
Figure 17-14: Watchdog Timer Mode Register 2 (WDTM2) Format
After reset: 67H
7 6
WDTM2 0 WDM21
WDM21 WDM20
0 0
0 1
1 -
Clock Selection," on page 708.
2. Although Watchdog timer 2 can be stopped just by stopping the operation of
Ring-OSC, set the WDTM2 register to 1FH to securely stop the timer (to avoid
selection of the main clock due to an erroneous write operation).
3. If the WDTM2 register is rewritten twice after reset, an overflow signal is forcibly
generated. But, the overflow signal does not occur, even if the WDTM2 register is
written twice after the watch dog timer is suspended.
4. To stop the operation of Watchdog timer 2, set the RSTP bit of the RCM register
to 1 (to stop Ring-OSC) and the WDTM2 register to 1FH.
User's Manual U16702EE3V2UD00
R/W Address: FFFFF6D0H
5 4 3
WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
Selection of operation mode of Watchdog Timer 2
Stops operation
Non-maskable interrupt request mode (generation of INTWDT2)
Reset mode (generation of WDTRES2)
2 1 0
707